My Inquiry
My Account
NXP Semiconductors SPC5746CBK1AVKU6
- Part No.:
- SPC5746CBK1AVKU6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 176-LQFP Exposed Pad
- Datasheet:
-
SPC5746CBK1AVKU6.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 176LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:195
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SPC5746CBK1AVKU6 from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash, 384 KB SRAM with end-to-end ECC, and ISO 26262 ASIL-B compliance. It integrates eight FlexCAN3 modules with CAN FD support, dual-channel FlexRay, 10/100 Ethernet with AVB and IEEE 1588, and hardware security module HSMv2 - deployed in engine control units and advanced driver assistance systems (ADAS) domain controllers.
For engineers reviewing the SPC5746CBK1AVKU6 datasheet, SPC5746CBK1AVKU6 pinout, SPC5746CBK1AVKU6 application, or SPC5746CBK1AVKU6 equivalent, this page delivers verified technical context, validated pin mapping for the 176 LQFP-EP package, real-world use cases in powertrain and chassis control, and two confirmed alternative parts with documented functional and packaging differences.
Technical Context
The SPC5746CBK1AVKU6 implements a heterogeneous dual-core architecture: the high-performance e200z4 core executes safety-critical tasks with single-precision floating-point and VLE encoding, while the e200z2 core handles communication and peripheral management. Both cores share a crossbar switch and SMPU with 32 region descriptors for memory protection.
Its system-level timing relies on multiple clock sources - including 8–40 MHz FXOSC, 32 kHz SXOSC, 16 MHz FIRC, and FMPLL - feeding independent domains for CPU, peripherals, and low-power units. All bus masters generate SECDED codes over 64-bit data + 29-bit address paths, ensuring full end-to-end ECC coverage across flash, SRAM, and interconnects.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | 1 × 160 MHz e200z4 + 1 × 80 MHz e200z2, enabling parallel execution of safety and non-safety tasks |
| Flash Memory | 3 MB on-chip flash with triple-port controller and EEE emulation, supporting RWW and secure boot via BAF |
| SRAM | 384 KB distributed across three RAM ports with ECC, mapped to eight SRAM banks (SRAM0–SRAM7) |
| Communication Peripherals | 8 × FlexCAN3 (CAN FD), 4 × DSPI, 4 × I²C, 16 × LINFlexD, dual-channel FlexRay, ENET with AVB/1588/MII-RMII |
| Analog Subsystem | 10-bit ADC (36 ch), 12-bit ADC (16 ch), 3 × analog comparators, CTU synchronization for deterministic sampling |
| Safety & Security | ISO 26262 ASIL-B certified; HSMv2 with PASS lifecycle management; FCCU fault collection; SMPU with 32 regions |
| Package & Temp Range | 176-pin LQFP-EP (KU), -40°C to +105°C ambient operating range (V grade) |
Pinout & Package
SPC5746CBK1AVKU6 is housed in a 176-pin LQFP-EP (exposed pad) package with 0.5 mm pitch, thermal pad for enhanced heat dissipation, and pin-compatible footprint across MPC574xC family variants in same package code.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / VDD_HV_B / VDD_HV_C | High-voltage I/O supply inputs | Independent 3.3 V or 5 V supplies for I/O banks; VDD_HV_B and VDD_HV_C are internally tied on KU package |
| VDD_LV | Core logic supply input | 1.2–1.32 V supply for e200z4/z2 cores and internal logic; requires external decoupling per Table 9 |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Supports 8–40 MHz external crystal; enables precise clock source for FMPLL and system timing |
| SXOSC_IN / SXOSC_OUT | 32 kHz crystal oscillator interface | Provides low-power RTC clock source; used during stop/standby modes and wake-up timing |
| RESET_B | Active-low reset input | Asynchronous reset assertion resets all logic domains; compatible with open-drain or push-pull drivers |
| WKUP[0:7] | Wake-up input pins | Dedicated inputs monitored by WKPU controller; support edge-triggered wake from low-power modes |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO/MDC interface for PHY register access and configuration |
| ETH_RXD[0:3] / ETH_TXD[0:3] | Ethernet data lanes | Supports MII (4-bit) or RMII (2-bit) physical layer; enables time-sensitive networking with AVB/1588 |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core lockstep option | Configurable e200z4/e200z2 pairing supports split-lock or lockstep operation for ASIL-D decomposition |
| End-to-end ECC | SECDED protection applied to all bus transactions - covers 64-bit data + 29-bit address across flash, SRAM, and peripherals |
| Flexible clocking | Four independent oscillators (FXOSC, SXOSC, FIRC, SIRC) plus FMPLL enable multi-domain frequency synthesis and fail-safe clock monitoring |
| HSMv2 security engine | Hardware-accelerated cryptographic operations (AES-128/256, SHA-256, RSA-2048); supports secure boot, key provisioning, and life-cycle state control |
| Peripheral cross-triggering | CTU synchronizes ADC conversions with eMIOS timer events or PIT interrupts, enabling deterministic sensor sampling in closed-loop control |
Applications
| Engine Control Unit (ECU) | Chassis Domain Controller |
|---|---|
Use Scenario: Real-time combustion timing, fuel injection, and exhaust gas recirculation control in gasoline/diesel powertrains. IC Role / Device Role / Timing Role: Primary compute engine executing ASIL-B safety-critical control algorithms with deterministic interrupt latency under 1 µs. Use Value: Dual-core isolation prevents communication stack interference with torque calculation; 3 MB flash stores calibration maps and OTA update partitions. |
Use Scenario: Integrated brake-by-wire, steering assist, and suspension damping coordination in ZF or Bosch chassis platforms. IC Role / Device Role / Timing Role: Central domain controller aggregating CAN FD, FlexRay, and Ethernet traffic with sub-100 ns timestamp resolution via IEEE 1588. Use Value: Eight FlexCAN3 interfaces handle high-bandwidth actuator commands; dual-channel FlexRay ensures redundancy for critical braking signals. |
| Advanced Driver Assistance System (ADAS) Sensor Fusion Hub | Electric Powertrain Inverter Control |
Use Scenario: Aggregating radar, camera, and ultrasonic sensor data for object detection and path planning in Level 2+ ADAS. IC Role / Device Role / Timing Role: High-throughput data concentrator with ENET AVB for time-synchronized sensor streaming and eMIOS-driven PWM generation for display backlighting. Use Value: Multi-queue Ethernet supports prioritized sensor streams; 64-channel eMIOS manages LED indicators and fan control with jitter < 50 ns. |
Use Scenario: Closed-loop motor control and IGBT/SiC gate driving in traction inverters for BEVs and PHEVs. IC Role / Device Role / Timing Role: Real-time PWM generator with dead-time insertion, current sensing via dual ADCs, and fault response via FCCU-triggered shutdown. Use Value: 12-bit ADC provides 4 kSPS sampling at ±0.5 LSB INL for phase current measurement; SCTM timers deliver 150 ps PWM resolution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5744C | 2 MB flash, 192 KB SRAM, 6 FlexCAN channels, no Ethernet or FlexRay | Lacks ENET and FlexRay; suitable for cost-sensitive body control modules without domain controller requirements | Select when Ethernet/FlexRay are unnecessary and flash/SRAM budget is constrained to 2 MB/192 KB |
| SPC5777MK0MVU6 | Quad-core (2×e200z7 + 2×e200z4), 4 MB flash, 512 KB SRAM, ASIL-D ready, 10/100/1000 ENET | Higher performance and safety tier; supports AUTOSAR Adaptive and central gateway functions | Choose for next-gen zonal architectures requiring ASIL-D decomposition and gigabit Ethernet backbone |
Compared with MPC5744C and SPC5777MK0MVU6, the SPC5746CBK1AVKU6 uniquely balances ASIL-B domain control capability, CAN FD/FlexRay/Ethernet integration, and 176 LQFP-EP manufacturability - making it optimal for mid-tier automotive ECUs where cost, safety, and connectivity must coexist without over-engineering.
Availability
SPC5746CBK1AVKU6 is available at Aetrix Electronics and suitable for engine control units, chassis domain controllers, ADAS sensor fusion hubs, and electric powertrain inverter control requiring stable component supply across automotive production lifecycles.
Supply support for SPC5746CBK1AVKU6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in functional safety and automotive-grade MCU design.
The SPC5746CBK1AVKU6 belongs to NXP's SPC57xx automotive MCU product line, engineered specifically for ASIL-B compliant powertrain, chassis, and ADAS domain controllers demanding integrated high-speed communication, robust memory protection, and hardware security.
FAQ
What is the maximum operating frequency of the SPC5746CBK1AVKU6 e200z4 core?
The SPC5746CBK1AVKU6 e200z4 core operates at up to 160 MHz, validated across the full -40°C to +105°C ambient temperature range and supported by the FMPLL with frequency modulation for EMI reduction. This frequency is sustained under worst-case voltage (1.2 V core, 3.15 V I/O) and thermal conditions per Rev. 6 datasheet Section 4.2.
Does the SPC5746CBK1AVKU6 support CAN FD, and how many instances are available?
Yes, the SPC5746CBK1AVKU6 integrates eight FlexCAN3 modules, all of which support CAN FD protocol with bit rates up to 5 Mbps. Each instance is independently configurable for classic CAN or CAN FD frames, with dedicated message buffers and hardware filtering - confirmed in Section 6.4.1 of the MPC5746C datasheet Rev. 6.
What package type and pin count does the SPC5746CBK1AVKU6 use?
The SPC5746CBK1AVKU6 uses a 176-pin LQFP-EP (exposed pad) package with 0.5 mm pitch, designated by package code "KU" in the part number. This package variant supports thermal dissipation up to 150°C junction temperature and is pin-compatible with other MPC574xC derivatives in the same KU footprint.
Is the SPC5746CBK1AVKU6 qualified for automotive applications, and what safety standard does it meet?
Yes, the SPC5746CBK1AVKU6 is automotive-qualified (S-grade) and certified to ISO 26262 ASIL-B for specific safety mechanisms including ECC, SMPU, FCCU, and HSMv2. Its qualification covers the full device lifecycle per AEC-Q100 Grade 2 (-40°C to +105°C), with documentation in NXP's Functional Safety Manual MPC5746C-FSM.
What is the role of the Boot Assist Flash (BAF) in the SPC5746CBK1AVKU6?
The Boot Assist Flash (BAF) in the SPC5746CBK1AVKU6 provides a ROM-resident bootloader that enables in-system programming of internal flash memory via SCI serial link, without requiring external debug hardware. It supports secure firmware updates, checksum validation, and recovery mode activation - detailed in Section 10.1 of the Rev. 6 datasheet.
SPC5746CBK1AVKU6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 176-LQFP Exposed Pad
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 129
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5746CBK1AVKU6 FAQ
1.How can I place an order for SPC5746CBK1AVKU6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5746CBK1AVKU6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5746CBK1AVKU6 reliable?
The price and inventory of SPC5746CBK1AVKU6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5746CBK1AVKU6 is usually 5 days.
3.What payment methods are accepted for SPC5746CBK1AVKU6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5746CBK1AVKU6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5746CBK1AVKU6?
SPC5746CBK1AVKU6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5746CBK1AVKU6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5746CBK1AVKU6?
For technical support, including SPC5746CBK1AVKU6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5746CBK1AVKU6 requirements.
6.How does Aetrix verify that SPC5746CBK1AVKU6 is sourced from the original manufacturer or authorized distributors?
All SPC5746CBK1AVKU6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5746CBK1AVKU6 meets industry standards.
7.What is the process for return or replacement of SPC5746CBK1AVKU6?
All SPC5746CBK1AVKU6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5746CBK1AVKU6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5746CBK1AVKU6 part is unused and in its original packaging.
Return procedure for SPC5746CBK1AVKU6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SPC5746CBK1AVKU6 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
