NXP Semiconductors SPC5746CHK1ACMJ6

Overview

SPC5746CHK1ACMJ6 from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash, 384 KB SRAM with end-to-end ECC, and integrated HSMv2 security module. It supports ISO 26262 ASIL-B functional safety and operates from –40°C to +85°C in a 256-pin MAPBGA package. It is designed for engine control units (ECUs), transmission control, and chassis domain controllers requiring deterministic real-time performance and secure boot.

For engineers reviewing the SPC5746CHK1ACMJ6 datasheet, SPC5746CHK1ACMJ6 pinout, SPC5746CHK1ACMJ6 application, or SPC5746CHK1ACMJ6 equivalent, this page delivers verified technical context-including dual-core clock domains, FlexCAN FD channel count, flash memory partitioning, SMPU region granularity, and HSMv2 cryptographic acceleration-enabling accurate ECU architecture validation and BOM selection.

Technical Context

The SPC5746CHK1ACMJ6 implements a heterogeneous dual-core Power Architecture® system: the e200z4 core handles high-intensity control tasks with single-precision floating-point support and 8 KB instruction/4 KB data cache, while the e200z2 core manages background services and communication stacks using VLE encoding for reduced code footprint. Both cores share a crossbar switch and SMPU with 32 region descriptors.

Its memory subsystem includes triple-ported 3 MB flash with three page buffers and 384 KB SRAM distributed across three RAM ports, all protected by SECDED ECC on all bus transactions. Clocking is managed via FMPLL, FXOSC (8–40 MHz), SXOSC (32 kHz), FIRC (16 MHz), and SIRC (128 kHz), with dedicated CMU and RTC.

Key Specifications

Pinout & Package

SPC5746CHK1ACMJ6 is housed in a 256-ball MAPBGA (package code MJ), 15 mm × 15 mm, 0.8 mm pitch, RoHS-compliant, with thermal pad. Pin assignment follows NXP's MPC5746C standard ballout for MJ package, supporting configurable I/O domains for FlexCAN, LINFlexD, Ethernet, and general-purpose GPIO.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar automotive microcontroller applications.

Compared with SPC5746CHK1ACMJ6, MPC5746CK1ACMJ6 omits HSMv2 and cannot meet ASIL-B security requirements, while SPC574S24K1MLQ1 reduces core count and FlexCAN channels - making SPC5746CHK1ACMJ6 the only option supporting full dual-core safety partitioning and 8-channel CAN FD in the MPC5746 family.

Availability

SPC5746CHK1ACMJ6 is available at Aetrix Electronics and suitable for engine control units, transmission control modules, and chassis domain controllers requiring stable component supply across automotive production lifecycles.

Supply support for SPC5746CHK1ACMJ6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Power Architecture® and functional safety.

The MPC5746C product line was developed specifically for ASIL-B automotive powertrain and chassis control applications, integrating dual-core real-time processing, hardware security, and robust analog/peripheral interfaces in a single die.

FAQ

What is the maximum operating frequency of each CPU core in the SPC5746CHK1ACMJ6?

The SPC5746CHK1ACMJ6 integrates two Power Architecture® cores: the e200z4 core runs at up to 160 MHz for high-intensity control tasks, and the e200z2 core operates at up to 80 MHz for auxiliary processing. Both frequencies are guaranteed under –40°C to +85°C ambient conditions with appropriate voltage regulation and thermal management. These clock speeds are defined in the device's FMPLL configuration and validated per NXP's MPC5746C Rev. 6 datasheet section 6.2.5.

Does the SPC5746CHK1ACMJ6 support CAN FD, and how many channels are available?

Yes, the SPC5746CHK1ACMJ6 supports CAN FD on all eight FlexCAN3 modules (FlexCAN0 through FlexCAN7), each capable of data rates up to 5 Mbps in FD mode. This capability is confirmed in the MPC5746C datasheet Table 1 and block diagram (Figure 1), and applies specifically to the SPC5746CHK1ACMJ6 variant with HSMv2 and full peripheral enablement.

What is the role of the Hardware Security Module (HSMv2) in the SPC5746CHK1ACMJ6?

The HSMv2 in the SPC5746CHK1ACMJ6 provides dedicated hardware acceleration for AES-128/256, SHA-256, RSA-2048, and ECDSA cryptographic operations, enabling secure boot, authenticated firmware updates, and key management without burdening the main e200z4/z2 cores. It is integral to achieving ISO 26262 ASIL-B compliance and is enabled in the SPC5746CHK1ACMJ6 variant per NXP's ordering guide and datasheet Section 2.1.

How much on-chip flash and SRAM does the SPC5746CHK1ACMJ6 include, and what protection mechanisms apply?

The SPC5746CHK1ACMJ6 includes 3 MB of on-chip flash memory and 384 KB of on-chip SRAM, both protected by end-to-end SECDED ECC across all bus transactions. Flash is organized into ten 256 KB blocks with RWW capability; SRAM is distributed across three ports. These values and ECC coverage are specified in the MPC5746C datasheet Sections 2 and 6.3, and apply to the SPC5746CHK1ACMJ6 as a member of the MPC5746C family with full memory enablement.

Which package type and pin count does the SPC5746CHK1ACMJ6 use?

The SPC5746CHK1ACMJ6 uses a 256-ball MAPBGA package (package code MJ), measuring 15 mm × 15 mm with 0.8 mm ball pitch and an exposed thermal pad. This package is explicitly assigned to the SPC5746CHK1ACMJ6 in NXP's ordering information (Section 3.2 of MPC5746C Rev. 6 datasheet) and supports full peripheral routing including FlexCAN FD, Ethernet MII/RMII, and dual FlexRay channels.