My Inquiry
My Account
NXP Semiconductors SPC5746CHK1AMKU6
- Part No.:
- SPC5746CHK1AMKU6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 176-LQFP Exposed Pad
- Datasheet:
-
SPC5746CHK1AMKU6.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 176LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:3,116
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SPC5746CHK1AMKU6 from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash, 384 KB SRAM with end-to-end ECC, and integrated HSMv2 security module. It supports ISO 26262 ASIL-B functional safety and operates from –40°C to +85°C in a 176-pin LQFP-EP package. It is designed for engine control units (ECUs), transmission control, and advanced driver assistance systems (ADAS) requiring deterministic real-time performance and secure boot.
For engineers reviewing the SPC5746CHK1AMKU6 datasheet, SPC5746CHK1AMKU6 pinout, SPC5746CHK1AMKU6 application, or SPC5746CHK1AMKU6 equivalent, this page delivers verified technical context, validated pin assignments, confirmed functional safety compliance, exact memory partitioning, and real-world automotive use cases - all grounded in NXP's MPC5746C Rev. 6 datasheet and official ordering documentation.
Technical Context
The SPC5746CHK1AMKU6 implements a tightly coupled dual-core architecture where the e200z4 core handles high-intensity control tasks (e.g., real-time torque calculation) and the e200z2 core manages background services (e.g., diagnostics, communication stack). Both cores share a crossbar switch enabling concurrent access to flash, RAM, and peripherals without arbitration bottlenecks.
Its clock system integrates FMPLL, FIRC (16 MHz), SIRC (128 kHz), FXOSC (8–40 MHz), and SXOSC (32 kHz), with Clock Monitor Unit (CMU) supervision and Real Time Counter (RTC) support. Memory protection is enforced via SMPU with 32 region descriptors and 16-byte granularity, while fault resilience is ensured by FCCU and SECDED ECC across all bus masters and memory interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | 1 × 160 MHz e200z4 + 1 × 80 MHz e200z2, both supporting VLE for code density optimization |
| Flash Memory | 3 MB on-chip flash with triple-port controller, EEE support, and RWW capability for safe firmware updates |
| SRAM | 384 KB distributed across three RAM ports with ECC coverage and optional 512 KB configuration |
| Functional Safety | ISO 26262 ASIL-B certified; includes FCCU, SMPU, and hardware watchdogs (SWT/STM/PIT) |
| Security | HSMv2 with PASS module for life-cycle management, secure boot, and cryptographic acceleration (AES/SHA/RSA) |
| Communication | 8 × FlexCAN3 with FD support, 16 × LINFlexD, 4 × DSPI, 4 × I²C, ENET (10/100 + AVB + IEEE 1588), Dual FlexRay |
| Analog Peripherals | 10-bit ADC (36 ch), 12-bit ADC (16 ch), 3 analog comparators, Cross Trigger Unit for synchronized sampling |
Pinout & Package
SPC5746CHK1AMKU6 is housed in a 176-pin LQFP-EP (exposed pad) package with 0.5 mm pitch, RoHS-compliant, and qualified for automotive AEC-Q100 Grade 2 operation. Pin assignments follow NXP's official MPC5746C pinout diagram (Rev. 6, Section 9.1), with dedicated power domains (VDD_HV_A/B/C, VDD_LV), analog supplies (VDD_HV_ADC0/1), and debug interface (JTAG/cJTAG).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A | High-voltage I/O supply | 3.3 V or 5.0 V main I/O rail; powers GPIO, LIN, CAN transceivers, and SPI peripherals |
| VDD_LV | Core logic supply | 1.2–1.32 V regulated supply for e200z4/z2 cores, cache, and internal logic; requires external decoupling |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Supports 8–40 MHz external crystal; enables precise timing for FMPLL and real-time control loops |
| JTAG_TCK / TMS / TDI / TDO | Nexus Class 3+ debug interface | IEEE-ISTO 5001-2008 compliant; enables non-intrusive trace, breakpoint, and core-level debugging |
| ENET_MDC / MDIO | Ethernet management interface | Provides PHY register access for IEEE 802.3 10/100 Ethernet with AVB and IEEE 1588 timestamping |
| FLEXCAN0_TX / RX | Primary CAN FD channel | Dedicated differential pair for CAN FD up to 5 Mbps; supports ISO 11898-1 physical layer compliance |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core lockstep-ready architecture | e200z4 and e200z2 cores operate independently but can be configured for redundancy-critical ASIL-D decomposition paths |
| End-to-end ECC protection | SECDED applied to all bus transactions (64-bit data + 29-bit address), covering flash, SRAM, and peripheral registers |
| Hardware Security Module v2 (HSMv2) | Offloads cryptographic operations (AES-128/256, SHA-256, RSA-2048), secure key storage, and anti-tamper monitoring |
| Configurable I/O domains | Independent voltage domains for FlexCAN, LINFlexD, Ethernet, and general-purpose I/O enable mixed-signal isolation |
| Boot Assist Flash (BAF) | Enables field firmware update via SCI serial link without external programmer; supports encrypted image loading |
Applications
| Engine Control Unit (ECU) | Transmission Control Module (TCM) |
|---|---|
Use Scenario: Real-time combustion timing, fuel injection pulse width, and knock detection in gasoline/diesel powertrains. IC Role / Device Role / Timing Role: Primary controller executing deterministic control algorithms at ≤100 µs loop intervals using e200z4 core and eMIOS timer subsystem. Use Value: 160 MHz e200z4 core with FP-Accelerator and 3 MB flash enables complex model-based control and over-the-air calibration storage. |
Use Scenario: Gear selection logic, clutch pressure modulation, and shift quality optimization in automatic and dual-clutch transmissions. IC Role / Device Role / Timing Role: Dual-core coordination: z4 handles torque vectoring calculations; z2 manages CAN FD communication with body domain and diagnostic logging. Use Value: 8 FlexCAN FD channels and 16 LINFlexD modules provide native connectivity to solenoid drivers, position sensors, and gear actuators. |
| Advanced Driver Assistance Systems (ADAS) Domain Controller | Electric Power Steering (EPS) Control Unit |
Use Scenario: Sensor fusion preprocessing (radar + camera triggers), adaptive cruise control actuation, and fail-operational path management. IC Role / Device Role / Timing Role: Safety-critical executor of ASIL-B functions with SMPU-enforced memory partitioning between perception and actuation software partitions. Use Value: ISO 26262 ASIL-B certification, FCCU fault collection, and HSMv2 secure boot ensure compliance with UN R155 and ISO/PAS 21448 (SOTIF). |
Use Scenario: Torque assist calculation, motor phase current control, and steering angle feedback processing in steer-by-wire architectures. IC Role / Device Role / Timing Role: High-bandwidth ADC sampling (12-bit @ 1 MSPS) synchronized via Cross Trigger Unit to eMIOS timers for precise motor commutation timing. Use Value: 12-bit ADC with 16 external channels and hardware-triggered conversion reduces MCU load and improves torque response latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5748G | Higher flash (4 MB), larger SRAM (512 KB), adds third e200z2 core; no HSMv2 - uses legacy HSM | Targeted at gateway ECUs requiring more protocol stacks (e.g., DoIP, SOME/IP); lacks ASIL-B certification for full HSM path | Select when needing >3 MB flash and multi-protocol routing; avoid if HSMv2 crypto acceleration or ASIL-B HSM path is mandatory. |
| SPC58NG84C3 | ARM Cortex-R52 dual-core (300 MHz), 4 MB flash, 1.5 MB SRAM, ASIL-D capable, supports virtualization | Designed for zonal architecture and AUTOSAR Adaptive; requires different toolchain (ARM GCC vs. Power Architecture GCC) | Select for next-gen E/E architecture requiring POSIX OS support or hypervisor-based partitioning; not drop-in compatible due to ISA and pinout differences. |
Compared with MPC5746C-based alternatives, SPC5746CHK1AMKU6 delivers optimal balance of ASIL-B compliance, CAN FD bandwidth, and mature Power Architecture tooling - making it preferred for cost-sensitive, high-volume powertrain applications where ecosystem stability outweighs raw compute uplift.
Availability
SPC5746CHK1AMKU6 is available at Aetrix Electronics and suitable for engine control units, transmission control modules, and ADAS domain controllers requiring stable component supply across automotive production lifecycles.
Supply support for SPC5746CHK1AMKU6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in functional safety and automotive-grade microcontrollers.
The MPC5746C product line was engineered specifically for ASIL-B automotive powertrain and chassis control applications, emphasizing deterministic real-time execution, end-to-end memory safety, and integrated hardware security for secure firmware updates and cryptographic services.
FAQ
What is the operating temperature range for SPC5746CHK1AMKU6?
SPC5746CHK1AMKU6 is rated for ambient operation from –40°C to +85°C (Grade C), validated per AEC-Q100 with junction temperature support up to 150°C. This range aligns with under-hood automotive environments and is specified in NXP's MPC5746C datasheet Rev. 6, Section 4.2.
Does SPC5746CHK1AMKU6 support CAN FD, and how many channels are available?
Yes, SPC5746CHK1AMKU6 supports CAN FD on all eight FlexCAN3 modules, each configurable for bit rates up to 5 Mbps in FD mode. This is confirmed in the "Communication" section of the MPC5746C datasheet Rev. 6 and Table 1 (Family Comparison), which lists "8 with optional CAN FD support" for MPC5746C.
What security features does SPC5746CHK1AMKU6 include?
SPC5746CHK1AMKU6 integrates HSMv2 with AES-128/256, SHA-256, and RSA-2048 acceleration, PASS module for device life-cycle management, and secure boot enforcement. These capabilities are documented in the "Security" section of the MPC5746C datasheet Rev. 6 and are enabled in the SPC5746CHK1AMKU6 variant per NXP's ordering guide.
Is SPC5746CHK1AMKU6 pin-compatible with other MPC5746x variants?
SPC5746CHK1AMKU6 uses the 176-pin LQFP-EP package (KU suffix), which shares identical mechanical and electrical pinout with all other MPC5746x devices in the same package option (e.g., MPC5746B, MPC5746C). However, feature enablement (e.g., HSM, RAM size) varies by part number - verify peripheral mapping in the specific variant's memory map tables.
What development tools are supported for SPC5746CHK1AMKU6?
SPC5746CHK1AMKU6 is supported by S32 Design Studio for Power Architecture, including compiler, debugger, and configuration tools. NXP also provides SPC5746C evaluation boards (e.g., SPC5746C-DB), AUTOSAR MCAL drivers, and functional safety libraries certified to ISO 26262 ASIL-B - all accessible via NXP's official developer portal.
SPC5746CHK1AMKU6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 176-LQFP Exposed Pad
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 129
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5746CHK1AMKU6 FAQ
1.How can I place an order for SPC5746CHK1AMKU6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5746CHK1AMKU6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5746CHK1AMKU6 reliable?
The price and inventory of SPC5746CHK1AMKU6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5746CHK1AMKU6 is usually 5 days.
3.What payment methods are accepted for SPC5746CHK1AMKU6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5746CHK1AMKU6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5746CHK1AMKU6?
SPC5746CHK1AMKU6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5746CHK1AMKU6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5746CHK1AMKU6?
For technical support, including SPC5746CHK1AMKU6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5746CHK1AMKU6 requirements.
6.How does Aetrix verify that SPC5746CHK1AMKU6 is sourced from the original manufacturer or authorized distributors?
All SPC5746CHK1AMKU6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5746CHK1AMKU6 meets industry standards.
7.What is the process for return or replacement of SPC5746CHK1AMKU6?
All SPC5746CHK1AMKU6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5746CHK1AMKU6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5746CHK1AMKU6 part is unused and in its original packaging.
Return procedure for SPC5746CHK1AMKU6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SPC5746CHK1AMKU6 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
