NXP Semiconductors SPC5746CHK1AMMJ6
- Part No.:
- SPC5746CHK1AMMJ6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 256-LBGA
- Datasheet:
-
SPC5746CHK1AMMJ6.pdf
- Description:
- IC MCU 32BIT 3MB FLSH 256MAPPBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,322
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SPC5746CHK1AMMJ6 from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash, 384 KB SRAM with end-to-end ECC, and integrated HSMv2 security module. It supports ISO 26262 ASIL-B functional safety and operates from –40°C to +125°C. Used in engine control units (ECUs) for real-time combustion management and diagnostics.
For engineers reviewing the SPC5746CHK1AMMJ6 datasheet, SPC5746CHK1AMMJ6 pinout, SPC5746CHK1AMMJ6 application, or SPC5746CHK1AMMJ6 equivalent, key selection criteria include dual-core deterministic timing, FlexCAN FD and Ethernet AVB support, hardware security for secure boot, and qualification for automotive powertrain systems requiring ASIL-B compliance.
Technical Context
The SPC5746CHK1AMMJ6 implements a crossbar switch architecture enabling concurrent access to flash, RAM, and peripherals by multiple bus masters-including both e200z4 and e200z2 cores, eDMA, and ENET. Its memory subsystem includes triple-ported 64-bit-wide flash controller with three page buffers and SMPU with 32 region descriptors for fine-grained memory protection.
Timing and safety are enforced via FMPLL with frequency modulation, RTC, 16 PITs, two STM modules, FCCU fault collection, and CMU clock monitoring. All bus transactions use SECDED (single error correction, double error detection) across 64-bit data and 29-bit address paths-covering core, DMA, and peripheral accesses.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | 1 × 160 MHz e200z4 (dual-issue, VLE, SPFP) + 1 × 80 MHz e200z2 (VLE) |
| Flash Memory | 3 MB on-chip, triple-ported, with EEE support and RWW capability |
| SRAM | 384 KB distributed across 8 ports, all protected by end-to-end ECC |
| Functional Safety | ISO 26262 ASIL-B certified; FCCU, SMPU, and lockstep-capable peripherals |
| Communication | 8 × FlexCAN3 with FD, 16 × LINFlexD, 4 × DSPI, 4 × I²C, ENET (10/100, AVB, IEEE 1588) |
| Security | HSMv2 with cryptographic acceleration, PASS lifecycle management, and secure boot enforcement |
| Package & Temp | 256-pin MAPBGA (MJ), –40°C to +125°C ambient operating range |
Pinout & Package
SPC5746CHK1AMMJ6 is housed in a 256-ball MAPBGA package (JEDEC MO-275AA), 17 mm × 17 mm, 0.8 mm pitch, thermally enhanced with exposed thermal pad. Pin assignment follows NXP's standard MPC5746C ballout for MJ package variant, supporting configurable I/O domains for FlexCAN, LIN, Ethernet, and general-purpose signals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / VDD_HV_B / VDD_HV_C | High-voltage IO supply rails | Independent 3.3 V or 5 V supplies for I/O banks; enable mixed-voltage interfacing |
| VDD_LV | Core logic supply | 1.2–1.32 V regulated input for e200z4/z2 cores and internal logic |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Supports 8–40 MHz external crystal for primary clock source with CMU monitoring |
| SXOSC_IN / SXOSC_OUT | 32 kHz real-time clock oscillator | Enables low-power RTC operation and wake-up from standby modes |
| FMPLL_REFCLK | PLL reference input | Accepts FXOSC, SXOSC, or FIRC as PLL reference for generating 160 MHz core clocks |
| ENET_MDC / ENET_MDIO | IEEE 802.3 management interface | Configures PHY registers and monitors link status for AVB-compliant Ethernet stack |
| FLEXCAN0_TX / FLEXCAN0_RX | Channel 0 CAN FD transceiver interface | Differential signaling compliant with ISO 11898-1:2015 up to 5 Mbps |
| WKPU_IN[0:7] | Wake-up input channels | Eight dedicated pins with programmable edge sensitivity for low-power mode exit |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core deterministic execution | e200z4 handles safety-critical control loops at 160 MHz; e200z2 manages communication stacks and diagnostics at 80 MHz-enabling ASIL-B decomposition |
| End-to-end ECC memory protection | SECDED applied to all bus transactions across flash, SRAM, and peripheral interfaces-ensuring data integrity without software overhead |
| Hardware Security Module v2 (HSMv2) | Offloads cryptographic operations (AES-128/256, SHA-256, RSA-2048), enforces secure boot, and manages key lifecycle per UNECE R155 requirements |
| FlexCAN FD with protocol acceleration | Eight independent CAN FD controllers supporting >5 Mbps data phase, CRC offload, and message RAM filtering-reducing CPU load in multi-bus ECU architectures |
| AVB-compliant Ethernet subsystem | 10/100 MII/RMII interface with IEEE 1722/1588 timestamping, multi-queue scheduling, and traffic shaping-enabling time-sensitive networking in domain controllers |
Applications
| Engine Control Unit (ECU) | Transmission Control Module (TCM) |
|---|---|
|
Use Scenario: Real-time fuel injection timing, spark advance calculation, and OBD-II diagnostics in gasoline/diesel powertrains. IC Role / Device Role / Timing Role: Primary controller executing ASIL-B safety-critical algorithms with deterministic latency under 10 µs interrupt response. Use Value: Dual-core separation allows lockstep-free safety partitioning while maintaining 160 MHz compute headroom for model-based control. |
Use Scenario: Gear shift actuation, clutch pressure control, and torque converter lockup coordination in 8-speed automatic transmissions. IC Role / Device Role / Timing Role: High-integrity motion controller synchronizing eMIOS PWM outputs, ADC sampling, and CAN FD feedback loops. Use Value: 64-channel eMIOS + 384 KB ECC SRAM enables precise 100 ns PWM resolution and jitter-free sensor acquisition. |
| Electric Power Steering (EPS) | Vehicle Domain Controller |
|
Use Scenario: Assist torque generation, motor position sensing, and fault-tolerant fail-safe operation during steering column actuation. IC Role / Device Role / Timing Role: Safety MCU managing torque path monitoring, BCTU-synchronized ADC conversions, and LINFlexD communication with sensors. Use Value: Integrated analog comparators and cross-trigger unit eliminate external signal conditioning, reducing BOM count and PCB area. |
Use Scenario: Centralized vehicle network node aggregating CAN FD, LIN, Ethernet AVB, and FlexRay traffic for ADAS and infotainment gateways. IC Role / Device Role / Timing Role: High-bandwidth interconnect hub with multi-queue ENET, 8 FlexCAN FD ports, and dual-channel FlexRay controller. Use Value: Concurrent access via crossbar switch ensures zero-contention throughput for 100+ Mbps aggregated traffic across domains. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5748G | Higher RAM (512 KB), additional HSM code/data blocks, same dual-core architecture and peripheral set | Better suited for complex OTA update stacks and larger secure firmware partitions | Select MPC5748G when >384 KB SRAM or extended HSM storage is required; otherwise SPC5746CHK1AMMJ6 offers optimal cost/performance for ASIL-B ECU designs |
| SPC58NG84C3 | Tri-core (e200z7 + dual e200z4), 4 MB flash, higher clock (200 MHz), AURIX-compatible toolchain | Targets ASIL-D systems requiring redundant computation paths and larger safety-certified code footprints | Choose SPC58NG84C3 only when ASIL-D decomposition or >160 MHz deterministic throughput is mandatory; SPC5746CHK1AMMJ6 remains preferred for cost-sensitive ASIL-B deployments |
Compared with MPC5748G and SPC58NG84C3, the SPC5746CHK1AMMJ6 delivers the most balanced integration of ASIL-B safety, dual-core determinism, and automotive-grade communication (CAN FD, AVB, FlexRay) in a thermally optimized 256-BGA package-making it the reference choice for mainstream powertrain and chassis ECUs.
Availability
SPC5746CHK1AMMJ6 is available at Aetrix Electronics and suitable for engine control units, transmission control modules, electric power steering systems, and vehicle domain controllers requiring stable component supply across automotive production lifecycles.
Supply support for SPC5746CHK1AMMJ6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in functional safety and embedded security.
The SPC5746CHK1AMMJ6 belongs to NXP's SPC57 family of automotive MCUs, designed specifically for ASIL-B powertrain and chassis control applications requiring high computational integrity, multi-protocol communication, and hardware-enforced security.
FAQ
What is the maximum operating temperature for the SPC5746CHK1AMMJ6?
The SPC5746CHK1AMMJ6 is qualified for operation from –40°C to +125°C ambient temperature, with junction temperature rated up to +150°C. This rating aligns with AEC-Q100 Grade 1 requirements and supports deployment in under-hood engine control environments where thermal stress is critical. The device includes integrated thermal monitoring and LVD/HVD circuits to ensure safe shutdown before exceeding limits.
Does the SPC5746CHK1AMMJ6 support CAN FD, and how many channels are available?
Yes, the SPC5746CHK1AMMJ6 integrates eight FlexCAN3 modules, all supporting CAN FD protocol with bit rates up to 5 Mbps in the data phase. Each channel features dedicated message RAM, hardware filtering, and CRC offload-enabling deterministic handling of high-bandwidth diagnostic and control frames without CPU intervention. This capability is confirmed in the MPC5746C datasheet Rev. 6, Section 6.4.2.
What security features does the SPC5746CHK1AMMJ6 include for secure boot and firmware updates?
The SPC5746CHK1AMMJ6 includes HSMv2 with AES-128/256, SHA-256, and RSA-2048 acceleration, plus Password and Device Security (PASS) for secure key provisioning and lifecycle management. Secure boot is enforced via immutable ROM bootloader that validates signed firmware images before execution. These capabilities meet UNECE R155 requirements and are documented in the MPC5746C Security Reference Manual.
Is the SPC5746CHK1AMMJ6 pin-compatible with other MPC5746x variants?
No, the SPC5746CHK1AMMJ6 uses the 256-ball MAPBGA (MJ) package, which is not pin-compatible with 100-BGA (MH) or 176-LQFP-EP (KU) variants. While electrical functionality is consistent across the MPC5746C family, ballout differs significantly between packages-requiring separate PCB layouts. Pin compatibility is only guaranteed within the same package code (e.g., MJ-to-MJ).
What development tools and debug interfaces are supported for the SPC5746CHK1AMMJ6?
The SPC5746CHK1AMMJ6 supports JTAG and cJTAG (IEEE 1149.7) for boundary scan and debug, with Nexus Class 3+ trace on both e200z4 and e200z2 cores. NXP's S32DS IDE, PE Micro Multilink Universal, and Lauterbach TRACE32 provide full visibility into dual-core execution, memory ECC status, and peripheral register states-enabling ASIL-B verification workflows per ISO 26262 Part 6.
SPC5746CHK1AMMJ6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 256-LBGA
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 178
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5746CHK1AMMJ6 FAQ
1.How can I place an order for SPC5746CHK1AMMJ6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5746CHK1AMMJ6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5746CHK1AMMJ6 reliable?
The price and inventory of SPC5746CHK1AMMJ6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5746CHK1AMMJ6 is usually 5 days.
3.What payment methods are accepted for SPC5746CHK1AMMJ6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5746CHK1AMMJ6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5746CHK1AMMJ6?
SPC5746CHK1AMMJ6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5746CHK1AMMJ6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5746CHK1AMMJ6?
For technical support, including SPC5746CHK1AMMJ6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5746CHK1AMMJ6 requirements.
6.How does Aetrix verify that SPC5746CHK1AMMJ6 is sourced from the original manufacturer or authorized distributors?
All SPC5746CHK1AMMJ6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5746CHK1AMMJ6 meets industry standards.
7.What is the process for return or replacement of SPC5746CHK1AMMJ6?
All SPC5746CHK1AMMJ6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5746CHK1AMMJ6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5746CHK1AMMJ6 part is unused and in its original packaging.
Return procedure for SPC5746CHK1AMMJ6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SPC5746CHK1AMMJ6 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

