NXP Semiconductors SPC5746CHK1AVKU6
- Part No.:
- SPC5746CHK1AVKU6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 176-LQFP Exposed Pad
- Datasheet:
-
SPC5746CHK1AVKU6.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SPC5746CHK1AVKU6 from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz Power Architecture® e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash, 384 KB SRAM with end-to-end ECC, and integrated HSMv2 security module. It supports ISO 26262 ASIL-B functional safety and targets engine control units (ECUs), transmission controllers, and battery management systems in 125°C ambient environments.
For engineers reviewing the SPC5746CHK1AVKU6 datasheet, SPC5746CHK1AVKU6 pinout, SPC5746CHK1AVKU6 application, or SPC5746CHK1AVKU6 equivalent, key selection criteria include dual-core deterministic timing, FlexCAN FD + Ethernet AVB connectivity, hardware security for secure boot and key management, and qualification for automotive AEC-Q100 Grade 1 (-40°C to +125°C).
Technical Context
The SPC5746CHK1AVKU6 implements a tightly coupled dual-CPU architecture with crossbar-switch interconnect enabling concurrent access to flash, RAM, and peripherals. Its memory subsystem includes triple-ported 3 MB flash with page buffers and 384 KB SRAM distributed across three ports, all protected by SECDED ECC for bus transactions and memory arrays.
Timing and safety are enforced via FMPLL clock generation, RTC, CMU, FCCU fault collection, SMPU with 32 region descriptors, and dedicated safety mechanisms including SWT, PIT-RTI, and STCU2 MBIST - all aligned to ISO 26262 ASIL-B requirements for automotive powertrain applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | e200z4 @ 160 MHz + e200z2 @ 80 MHz, dual-issue and single-issue respectively, supporting VLE for code density |
| Flash Memory | 3 MB on-chip flash with triple-port controller, EEE support, and RWW capability for background programming |
| RAM | 384 KB on-chip SRAM across three ports, all protected by end-to-end ECC (SECDED) |
| Functional Safety | ISO 26262 ASIL-B certified; includes FCCU, SMPU, SWT, PIT-RTI, STCU2, and lockstep-capable peripherals |
| Security | HSMv2 with PASS module for secure boot, cryptographic acceleration (AES/SHA/RSA), and life-cycle management |
| Communication | 8 × FlexCAN FD, 16 × LINFlexD, 4 × DSPI, 4 × I²C, ENET (10/100 MII/RMII + IEEE 1588 + AVB), dual FlexRay |
| Analog | 10-bit ADC (68 ch), 12-bit ADC (31 ch), 3 analog comparators, CTU for synchronized sampling |
Pinout & Package
SPC5746CHK1AVKU6 is housed in a 176-pin LQFP-EP package (exposed pad) with 0.5 mm pitch, optimized for automotive thermal and mechanical reliability. Pin functions are organized into dedicated I/O domains for FlexCAN, LIN, Ethernet, and general-purpose use, with configurable voltage domains (3.3 V / 5 V).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / B / C | High-voltage I/O supply rails | Independent 3.3 V or 5 V supplies for I/O banks; enable mixed-voltage interfacing with sensors, transceivers, and legacy ECUs |
| VDD_LV | Core logic supply | 1.2–1.32 V regulated core voltage; supports low-power operation and dynamic voltage scaling |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | 8–40 MHz external crystal input; enables precise clock source for FMPLL and real-time control loops |
| SXOSC_IN / SXOSC_OUT | 32 kHz crystal interface | Low-power RTC and wake-up timing source; supports stop-mode operation with <1 µA current draw |
| RESET_B | Active-low reset input | Asynchronous reset assertion; initiates POR sequence and clears internal state, including HSM and memory protection units |
| WKPU[0:7] | Wake-up pin inputs | Dedicated low-power wake-up sources; trigger exit from stop/doze modes without full CPU restart |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core deterministic execution | Independent e200z4 and e200z2 cores allow separation of safety-critical (ASIL-B) and non-safety tasks without software partitioning overhead |
| End-to-end ECC protection | SECDED coverage across all bus masters, flash, SRAM, and peripheral registers prevents silent data corruption in harsh automotive environments |
| Hardware Security Module v2 | HSMv2 provides tamper-resistant key storage, AES-128/256, SHA-256, RSA-2048 acceleration, and secure boot verification per UNECE R155 requirements |
| Configurable I/O domains | Per-bank voltage and slew-rate control enables direct interfacing with 3.3 V CAN transceivers, 5 V LIN drivers, and 1.8 V digital sensors |
| FlexCAN FD + Ethernet AVB | Simultaneous high-speed CAN FD (5 Mbps) and time-sensitive networking (IEEE 1588 PTP, AVB QoS) support domain-centralized vehicle architectures |
Applications
| Engine Control Unit (ECU) | Transmission Control Module (TCM) |
|---|---|
Use Scenario: Real-time combustion timing, fuel injection pulse width, and knock detection in gasoline/diesel powertrains. IC Role / Device Role / Timing Role: Primary controller executing ASIL-B safety-critical algorithms with deterministic latency under 10 µs interrupt response. Use Value: Dual-core isolation ensures engine torque control remains active during diagnostic or communication interrupts; ECC prevents corrupted spark timing tables. |
Use Scenario: Clutch engagement scheduling, gear shift logic, and hydraulic pressure regulation in automatic transmissions. IC Role / Device Role / Timing Role: Safety-managed actuator driver coordinating solenoid PWM, CAN FD feedback, and fault-tolerant position sensing. Use Value: SMPU-enforced memory partitioning isolates transmission firmware from infotainment updates; HSMv2 secures calibration data against unauthorized reprogramming. |
| Battery Management System (BMS) | Electric Power Steering (EPS) |
Use Scenario: Cell voltage monitoring, thermal runaway prediction, and SOC/SOH estimation in 400–800 V traction battery packs. IC Role / Device Role / Timing Role: High-precision analog acquisition hub synchronizing 68-channel ADC sampling with eMIOS timer triggers for cell balancing control. Use Value: 12-bit ADC with CTU enables sub-1 mV accuracy across 96 cells; ECC-protected flash retains calibrated lookup tables through 10,000+ charge cycles. |
Use Scenario: Torque assist calculation, motor phase commutation, and road feel emulation in steer-by-wire systems. IC Role / Device Role / Timing Role: Real-time motor controller with dual-core lockstep mode for torque path validation and independent watchdog supervision. Use Value: e200z4 handles FOC calculations at 20 kHz PWM rate; e200z2 runs CAN FD diagnostics and EPS-specific safety monitors with <50 ns jitter. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5748G | Higher flash (4 MB), larger SRAM (512 KB), adds third e200z2 core; no HSMv2 - uses separate security co-processor | Targeted at zonal gateways requiring richer OS support and multi-domain virtualization | Select MPC5748G when >3 MB flash or hypervisor-ready memory layout is required; SPC5746CHK1AVKU6 offers tighter cost/performance for ECU-class control |
| SPC58NG84C3 | ARM Cortex-R5F dual-core (300 MHz), 4 MB flash, 1.5 MB RAM, ASIL-D capable, no FlexRay, adds PCIe and USB | Designed for next-gen ADAS domain controllers needing higher compute throughput and heterogeneous processing | Choose SPC58NG84C3 for ASIL-D safety integrity or ARM ecosystem compatibility; SPC5746CHK1AVKU6 maintains Power Architecture toolchain continuity and proven ECU qualification |
Compared with MPC5748G and SPC58NG84C3, the SPC5746CHK1AVKU6 delivers optimal balance of ASIL-B compliance, automotive I/O integration (FlexRay + CAN FD + LIN), and production-proven qualification - making it the preferred choice for cost-sensitive, thermally constrained powertrain ECUs where HSMv2-based secure boot is mandatory.
Availability
SPC5746CHK1AVKU6 is available at Aetrix Electronics and suitable for engine control units, transmission control modules, battery management systems, and electric power steering applications requiring stable component supply across extended automotive lifecycles.
Supply support for SPC5746CHK1AVKU6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in functional safety and automotive-grade microcontrollers.
The SPC5746CHK1AVKU6 belongs to NXP's SPC57 family of automotive MCUs, engineered specifically for powertrain and chassis control applications demanding ASIL-B compliance, real-time determinism, and integrated hardware security.
FAQ
What is the operating temperature range for the SPC5746CHK1AVKU6?
The SPC5746CHK1AVKU6 is qualified for automotive Grade 1 operation, supporting ambient temperatures from –40°C to +125°C. This rating is validated per AEC-Q100 and applies to all core, memory, and peripheral functions under specified supply conditions (VDD_HV = 3.3 V or 5 V, VDD_LV = 1.2–1.32 V). Junction temperature must not exceed 150°C during operation.
Does the SPC5746CHK1AVKU6 support CAN FD, and how many channels are available?
Yes, the SPC5746CHK1AVKU6 integrates eight FlexCAN3 modules, all supporting CAN FD protocol with data rates up to 5 Mbps. Each channel operates independently with programmable bit timing, message filtering, and hardware FIFOs - enabling simultaneous communication with multiple ECUs in modern vehicle networks without software arbitration overhead.
How is functional safety implemented in the SPC5746CHK1AVKU6?
The SPC5746CHK1AVKU6 achieves ISO 26262 ASIL-B compliance through integrated hardware safety mechanisms: Fault Collection and Control Unit (FCCU), System Memory Protection Unit (SMPU), dual watchdog timers (SWT), periodic interrupt timers (PIT), STCU2 for MBIST, and end-to-end ECC on all memory and bus transactions. These features are documented in NXP's FS Functional Safety Manual for MPC5746C.
What package type and pin count does the SPC5746CHK1AVKU6 use?
The SPC5746CHK1AVKU6 uses a 176-pin LQFP-EP (lead-free, exposed pad) package with 0.5 mm pitch. The exposed thermal pad enhances heat dissipation in high-power automotive applications and requires proper PCB land pattern design per NXP's SPC5746C Hardware Design Guide Rev. 3.
Is the SPC5746CHK1AVKU6 pin-compatible with other members of the MPC5746C family?
No - the SPC5746CHK1AVKU6 is not pin-compatible with other MPC5746C variants such as those in BGA packages (e.g., MJ or MN suffixes). Its KU suffix denotes the 176 LQFP-EP package, which has distinct pin mapping, power distribution, and thermal pad configuration versus 256/324 BGA variants. Migration requires PCB redesign and signal integrity revalidation.
SPC5746CHK1AVKU6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 176-LQFP Exposed Pad
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 129
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5746CHK1AVKU6 FAQ
1.How can I place an order for SPC5746CHK1AVKU6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5746CHK1AVKU6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5746CHK1AVKU6 reliable?
The price and inventory of SPC5746CHK1AVKU6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5746CHK1AVKU6 is usually 5 days.
3.What payment methods are accepted for SPC5746CHK1AVKU6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5746CHK1AVKU6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5746CHK1AVKU6?
SPC5746CHK1AVKU6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5746CHK1AVKU6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5746CHK1AVKU6?
For technical support, including SPC5746CHK1AVKU6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5746CHK1AVKU6 requirements.
6.How does Aetrix verify that SPC5746CHK1AVKU6 is sourced from the original manufacturer or authorized distributors?
All SPC5746CHK1AVKU6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5746CHK1AVKU6 meets industry standards.
7.What is the process for return or replacement of SPC5746CHK1AVKU6?
All SPC5746CHK1AVKU6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5746CHK1AVKU6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5746CHK1AVKU6 part is unused and in its original packaging.
Return procedure for SPC5746CHK1AVKU6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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