NXP Semiconductors SPC5746CK1AMKU6
- Part No.:
- SPC5746CK1AMKU6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 176-LQFP Exposed Pad
- Datasheet:
-
SPC5746CK1AMKU6.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,450
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SPC5746CK1AMKU6 from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash, 384 KB SRAM with end-to-end ECC, and integrated HSMv2 security module. It supports ISO 26262 ASIL-B functional safety and targets engine control units, transmission controllers, and battery management systems in 12 V/48 V hybrid vehicles.
For engineers reviewing the SPC5746CK1AMKU6 datasheet, SPC5746CK1AMKU6 pinout, SPC5746CK1AMKU6 application, or SPC5746CK1AMKU6 equivalent, key selection criteria include dual-core deterministic timing, FlexCAN FD + FlexRay + Ethernet AVB connectivity, hardware security for secure boot and key management, and qualification for -40°C to +125°C ambient operation in automotive powertrain applications.
Technical Context
The SPC5746CK1AMKU6 implements a crossbar switch architecture enabling concurrent access to flash, RAM, and peripherals by multiple bus masters-including both e200z4 and e200z2 cores, eDMA, and ENET. Its memory subsystem includes triple-ported 3 MB flash with page buffers and 384 KB SRAM distributed across three ports, all protected by SECDED ECC on 64-bit data + 29-bit address paths.
Timing and safety are enforced via FMPLL clock generation (8–40 MHz FXOSC input), Clock Monitor Unit (CMU), System Memory Protection Unit (SMPU) with 32 region descriptors, and Fault Collection and Control Unit (FCCU). The device integrates eight FlexCAN3 modules with CAN FD support, dual-channel FlexRay 2.1, and 10/100 Ethernet with IEEE 1588 and AVB multi-queue capability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160 MHz e200z4 + 80 MHz e200z2, both supporting VLE and single-precision floating-point |
| Flash Memory | 3 MB on-chip flash with triple-port controller, ECC protection, and RWW partitions for real-time firmware updates |
| SRAM | 384 KB distributed across three RAM ports, all protected by end-to-end SECDED ECC |
| Functional Safety | ISO 26262 ASIL-B certified; includes FCCU, SMPU, and lockstep-capable peripherals for fault detection |
| Communication Interfaces | 8 × FlexCAN3 (CAN FD), 2 × FlexRay 2.1, 1 × ENET (10/100 + IEEE 1588 + AVB), 4 × DSPI, 4 × I²C, 16 × LINFlexD |
| Security | HSMv2 with cryptographic acceleration (AES-128/256, SHA-256, RSA-2048), PASS lifecycle management, and secure boot enforcement |
| Package & Pin Count | 176-pin LQFP-EP (KU suffix), thermally enhanced for automotive under-hood mounting |
Pinout & Package
SPC5746CK1AMKU6 is housed in a 176-pin LQFP-EP (exposed pad) package, optimized for thermal dissipation in high-temperature automotive environments. Pin assignment follows NXP's MPC5746C family layout with dedicated domains for FlexCAN, LINFlexD, Ethernet, and configurable I/O.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / VDD_HV_B / VDD_HV_C | High-voltage I/O supply rails | Independent 3.3 V or 5 V supplies for I/O banks; enable mixed-voltage interfacing with sensors, transceivers, and actuators |
| VDD_LV | Core logic supply | 1.2–1.32 V regulated core voltage; supports dynamic voltage scaling and low-power modes |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | 8–40 MHz external crystal input for primary clock source; enables precise timing for engine control loops |
| FMPLL_REFCLK | FMPLL reference clock input | Accepts 8–40 MHz external or internal (FIRC/SIRC) clock; generates stable 160 MHz core clock with jitter < ±50 ps |
| CAN0_TX / CAN0_RX | FlexCAN0 differential transceiver interface | Direct connection to external CAN FD transceiver (e.g., TJA1044); supports bit rates up to 5 Mbps |
| ETH_MDIO / ETH_MDC / ETH_RXD[0:3] / ETH_TXD[0:3] | Ethernet physical layer interface | RMII/MII-compliant signals for 10/100 Ethernet; supports IEEE 1588 timestamping and AVB traffic shaping |
| JTAG_TCK / JTAG_TMS / JTAG_TDI / JTAG_TDO | Nexus Class 3+ debug interface | IEEE-ISTO 5001-2008 compliant; enables real-time trace, non-intrusive debugging, and calibration during runtime |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core deterministic execution | e200z4 handles safety-critical control loops (e.g., fuel injection timing), while e200z2 manages diagnostics, communication stacks, and UI tasks-without resource contention |
| End-to-end ECC protection | SECDED coverage across all bus transactions (cores, DMA, peripherals) prevents silent data corruption in flash, SRAM, and interconnects |
| Hardware Security Module v2 (HSMv2) | Offloads cryptographic operations (AES, SHA, RSA) from main cores; enforces secure boot, key provisioning, and anti-rollback policies |
| Flexible clock domain management | FMPLL + CMU + RTC + multiple IRC sources allow independent clock gating, frequency modulation, and fail-safe clock switching during faults |
| Automotive-grade peripheral integration | 8 CAN FD channels, dual FlexRay, Ethernet AVB, and 16 LIN interfaces eliminate need for external protocol bridges in ECU consolidation |
Applications
| Engine Control Unit (ECU) | Electric Power Steering (EPS) |
|---|---|
Use Scenario: Real-time combustion timing, air-fuel ratio control, and knock detection in gasoline/diesel ICE platforms. IC Role / Device Role / Timing Role: Primary controller executing ASIL-B safety-critical algorithms with sub-microsecond interrupt latency and deterministic cycle counts. Use Value: Dual-core separation isolates safety logic (e200z4) from diagnostics (e200z2), while 8 FlexCAN FD channels handle sensor fusion and actuator feedback at 2–5 Mbps. |
Use Scenario: Torque assist calculation, motor position control, and fault response in 12 V EPS systems with torque sensor and BLDC motor. IC Role / Device Role / Timing Role: Central motion controller synchronizing eMIOS PWM outputs, ADC sampling, and CAN FD status reporting within 100 µs deadlines. Use Value: 64-channel eMIOS + 12-bit ADC + cross-trigger unit enables precise motor phase alignment; HSMv2 secures firmware updates over CAN. |
| 48 V Mild Hybrid Battery Management | Vehicle Domain Controller Gateway |
Use Scenario: Cell voltage monitoring, state-of-charge estimation, thermal management, and contactor control in 48 V Li-ion battery packs. IC Role / Device Role / Timing Role: Safety-certified BMS master managing isolation, balancing, and communication with pack-level CAN FD and LIN networks. Use Value: 384 KB ECC-protected SRAM stores redundancy-critical BMS state tables; SMPU enforces memory partitioning between safety and non-safety tasks. |
Use Scenario: Aggregating and routing messages between CAN FD, FlexRay, Ethernet AVB, and LIN domains in zonal architectures. IC Role / Device Role / Timing Role: High-throughput gateway processor performing protocol translation, time-synchronized message forwarding, and firewall filtering. Use Value: Crossbar switch + eDMA enables concurrent 8× CAN FD + 2× FlexRay + ENET traffic; fractional clock dividers synchronize audio/video streams over SAI. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5748G | Higher flash (4 MB) and RAM (512 KB), adds third e200z2 core; no HSMv2, only basic PASS security | Better suited for complex ADAS domain controllers requiring larger code footprint but lower security assurance | Select MPC5748G when additional memory and compute headroom outweigh HSMv2 requirements |
| S32K344 | ARM Cortex-M7 + M33 dual-core; 3 MB flash, 512 KB RAM, ASIL-D capable, no FlexRay or Ethernet AVB | Targeted at chassis/safety ECUs needing highest ASIL level but lacking legacy automotive bus requirements | Choose S32K344 for new designs prioritizing ARM ecosystem and ASIL-D, not FlexRay/Ethernet AVB |
Compared with MPC5746C-based alternatives, SPC5746CK1AMKU6 uniquely combines Power Architecture deterministic timing, FlexRay 2.1, Ethernet AVB, and HSMv2 in a single 176-pin LQFP package-making it optimal for consolidating legacy and next-gen automotive networks without compromising safety or security certification.
Availability
SPC5746CK1AMKU6 is available at Aetrix Electronics and suitable for engine control units, electric power steering systems, and 48 V mild hybrid battery management requiring stable component supply across extended automotive product lifecycles.
Supply support for SPC5746CK1AMKU6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in functional safety and automotive-grade microcontrollers.
The MPC5746C product line was designed specifically for ASIL-B powertrain and chassis applications, integrating dual Power Architecture cores, hardware security, and automotive serial buses to replace discrete MCU + ASIC combinations in modern ECUs.
FAQ
What is the operating temperature range for the SPC5746CK1AMKU6?
The SPC5746CK1AMKU6 is qualified for ambient operation from –40°C to +125°C, meeting AEC-Q100 Grade 1 requirements. This range supports under-hood deployment in engine control units and transmission control modules where junction temperatures may reach 150°C. The device includes integrated thermal monitoring and automatic throttling to maintain reliability at maximum ambient conditions.
Does the SPC5746CK1AMKU6 support CAN FD, and how many channels are available?
Yes, the SPC5746CK1AMKU6 integrates eight FlexCAN3 modules, all supporting CAN FD with data rates up to 5 Mbps. Each channel operates independently with configurable bit timing, message filtering, and hardware FIFOs. This enables simultaneous communication with multiple high-bandwidth nodes-such as engine sensors, transmission controllers, and ADAS cameras-without software overhead.
How does the Hardware Security Module (HSMv2) in the SPC5746CK1AMKU6 function?
The HSMv2 in the SPC5746CK1AMKU6 is a dedicated security co-processor that executes cryptographic operations (AES-128/256, SHA-256, RSA-2048) independently of the main cores. It enforces secure boot, manages key lifecycles via PASS, and provides tamper-resistant storage for secrets. All HSMv2 interactions occur through defined APIs, isolating security-critical functions from application firmware running on the e200z4/z2 cores.
What package type and pin count does the SPC5746CK1AMKU6 use?
The SPC5746CK1AMKU6 uses a 176-pin LQFP-EP (leadless quad flat package with exposed pad) package, designated by the "KU" suffix in the part number. The exposed thermal pad improves heat dissipation in high-power automotive applications and requires solder paste stencil design per NXP's AN4923 guidelines for reliable mechanical and thermal performance.
Is the SPC5746CK1AMKU6 compatible with NXP's S32DS IDE and configuration tools?
No-the SPC5746CK1AMKU6 is based on Power Architecture e200z cores and requires NXP's older S32 Design Studio for Power Architecture (formerly Codewarrior for MCU), not the ARM-based S32DS IDE. Configuration is performed using Processor Expert and the MPC5746C-specific configuration tools, with debug support via Nexus Class 3+ JTAG/cJTAG interfaces.
SPC5746CK1AMKU6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 176-LQFP Exposed Pad
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 129
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5746CK1AMKU6 FAQ
1.How can I place an order for SPC5746CK1AMKU6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5746CK1AMKU6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5746CK1AMKU6 reliable?
The price and inventory of SPC5746CK1AMKU6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5746CK1AMKU6 is usually 5 days.
3.What payment methods are accepted for SPC5746CK1AMKU6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5746CK1AMKU6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5746CK1AMKU6?
SPC5746CK1AMKU6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5746CK1AMKU6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5746CK1AMKU6?
For technical support, including SPC5746CK1AMKU6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5746CK1AMKU6 requirements.
6.How does Aetrix verify that SPC5746CK1AMKU6 is sourced from the original manufacturer or authorized distributors?
All SPC5746CK1AMKU6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5746CK1AMKU6 meets industry standards.
7.What is the process for return or replacement of SPC5746CK1AMKU6?
All SPC5746CK1AMKU6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5746CK1AMKU6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5746CK1AMKU6 part is unused and in its original packaging.
Return procedure for SPC5746CK1AMKU6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SPC5746CK1AMKU6 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

