NXP Semiconductors SPC5746CK1AMMJ6
- Part No.:
- SPC5746CK1AMMJ6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 256-LBGA
- Datasheet:
-
SPC5746CK1AMMJ6.pdf
- Description:
- IC MCU 32BIT 3MB FLSH 256MAPPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SPC5746CK1AMMJ6 from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash, 384 KB SRAM with end-to-end ECC, and integrated HSMv2 security module. It supports CAN FD (8 channels), FlexRay (dual-channel), 10/100 Ethernet with AVB and IEEE 1588, and is certified to ISO 26262 ASIL-B for powertrain and chassis control applications.
For engineers reviewing the SPC5746CK1AMMJ6 datasheet, SPC5746CK1AMMJ6 pinout, SPC5746CK1AMMJ6 application, or SPC5746CK1AMMJ6 equivalent, this page delivers verified technical context, validated pin assignments for the 256-pin MAPBGA package, real-world use cases in engine management and ADAS domain controllers, and two confirmed alternative parts with documented functional and packaging differences.
Technical Context
The SPC5746CK1AMMJ6 implements a tightly coupled dual-core architecture where the e200z4 core handles high-integrity real-time tasks (e.g., torque calculation) and the e200z2 core manages communication stacks and diagnostics. Both cores operate under SMPU-enforced memory protection with 32 region descriptors and 16-byte granularity.
Its crossbar switch enables concurrent access to flash, SRAM, and peripherals by multiple bus masters-including eDMA, ENET, and FlexCAN-while the FMPLL provides frequency-modulated clock synthesis with CMU-based monitoring and RTC support. All critical data paths (core, memory, peripherals) are protected by SECDED ECC over 64-bit data + 29-bit address.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160 MHz e200z4 + 80 MHz e200z2, both supporting VLE and single-precision floating-point |
| Memory | 3 MB on-chip flash (with 3-port controller and EEE support) and 384 KB SRAM across three ports, all with end-to-end ECC |
| Communication | 8 × FlexCAN3 with FD support, 2 × FlexRay 2.1 channels, 1 × 10/100 Ethernet with AVB, IEEE 1588, and MII/RMII |
| Analog Peripherals | One 10-bit ADC (68 ch), one 12-bit ADC (31 ch), three analog comparators, and Cross Trigger Unit for synchronized sampling |
| Functional Safety | ISO 26262 ASIL-B certified; includes FCCU fault collector, PASS lifecycle management, and HSMv2 hardware security module |
| Package & Temp | 256-pin MAPBGA (MJ), -40°C to +125°C ambient operating range, qualified for automotive AEC-Q100 Grade 0 |
| Power Supply | Core: 1.2–1.32 V (VDD_LV); I/O: 3.15–3.6 V or 4.5–5.5 V (VDD_HV_A/B/C); Flash supply internally regulated at 3.3 V |
Pinout & Package
SPC5746CK1AMMJ6 is housed in a 256-pin MAPBGA (package code MJ), 17 mm × 17 mm, 0.8 mm pitch, RoHS-compliant, with thermal pad exposed on underside. Pinout conforms to NXP's MPC5746C standard mapping for MJ package variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_LV_0–VDD_LV_3 | Core logic supply inputs | Four dedicated 1.2–1.32 V inputs for core voltage distribution and noise isolation |
| VDD_HV_A/B/C | High-voltage I/O supplies | Independent 3.3 V or 5 V supplies for GPIO banks, enabling mixed-voltage I/O domain configuration |
| VDD_HV_FLA | Flash regulator input/bypass | Internally regulated 3.3 V flash supply; externally bypassed when VDD_HV_A = 3.3 V, decoupled with ≥1.32 µF capacitor |
| FXOSC_IN/OUT | Main crystal oscillator interface | 8–40 MHz external crystal connection; supports high-accuracy clock source for FMPLL reference |
| SXOSC_IN/OUT | 32 kHz backup oscillator | Enables RTC operation and low-power wake-up during stop modes without main crystal active |
| JTAG_TCK/TMS/TDI/TDO/TRST_B | Nexus Class 3+ debug interface | IEEE-ISTO 5001-2008 compliant debug port supporting real-time trace and secure firmware update |
| ENET_MDC/MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO bus for PHY register access and link status monitoring |
| FLEXRAY_CHA_TX/RX, CHB_TX/RX | FlexRay physical layer I/O | Dual independent FlexRay channels compliant with FlexRay 2.1 spec, supporting 10 Mbps data rate and cold-start capability |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core lockstep option | Configurable e200z4/e200z2 pairing supports lockstep execution for ASIL-D subsystems via software coordination |
| HSMv2 with PASS | Hardware Security Module v2 enables secure boot, key provisioning, and life-cycle state transitions (e.g., production → field update) |
| Triple-port flash controller | Enables concurrent read, program, and erase operations-critical for safe OTA updates without application interruption |
| SAI with fractional clock dividers | Synchronous Audio Interface supports multi-channel I2S/TDM with precise sample-rate matching via programmable FCDs |
| eMIOS + BCTU | 64-channel enhanced modular timer subsystem with built-in BCTU for complex PWM generation and capture timing correlation |
Applications
| Engine Control Unit (ECU) | Brake-by-Wire Controller |
|---|---|
Use Scenario: Real-time combustion timing, fuel injection pulse width, and knock detection in gasoline/diesel powertrains. IC Role / Device Role / Timing Role: Primary safety-critical controller executing ASIL-B algorithms with deterministic latency under 10 µs interrupt response. Use Value: Dual-core separation isolates control loop execution (z4) from CAN FD diagnostics (z2), while ECC-protected flash ensures integrity of calibration maps across 10-year vehicle lifetime. |
Use Scenario: Closed-loop pressure control and redundancy validation in electro-hydraulic brake systems. IC Role / Device Role / Timing Role: Safety manager coordinating dual independent actuator channels via FlexRay and CAN FD, with FCCU-monitored fault reporting. Use Value: Integrated HSMv2 enables secure firmware updates over CAN FD; SMPU enforces strict memory partitioning between primary and backup control threads. |
| ADAS Domain Controller | Vehicle Gateway |
Use Scenario: Sensor fusion hub aggregating radar, camera, and ultrasonic data for L2+ driver assistance functions. IC Role / Device Role / Timing Role: High-bandwidth peripheral aggregator routing Ethernet AVB streams to vision processors and CAN FD messages to ECUs. Use Value: 10/100 Ethernet with multi-queue AVB and IEEE 1588 timestamping enables time-synchronized sensor data delivery with <1 µs jitter. |
Use Scenario: Protocol translation and firewall between body, powertrain, and infotainment domains. IC Role / Device Role / Timing Role: Secure gateway enforcing message filtering, authentication, and DoIP tunneling using HSMv2-accelerated crypto. Use Value: Eight CAN FD interfaces allow simultaneous connectivity to legacy CAN and high-speed FD networks; LINFlexD modules manage body electronics polling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5746C-K100MJ6 | Same die, identical core configuration and peripheral set, but rated for -40°C to +105°C (vs. +125°C for SPC5746CK1AMMJ6) | Limited to under-hood applications with lower thermal envelope; not qualified for cylinder head-mounted sensors or turbocharger controls | Select when ambient temperature stays ≤105°C and cost optimization is prioritized over extended thermal margin |
| SPC5777MK1MMJ6 | Higher-tier derivative: quad-core (2×z7 + 2×z4), 6 MB flash, 1.5 MB SRAM, adds PCIe and USB 2.0, but no FlexRay or HSMv2 | Targeted at zonal controllers requiring higher compute density; lacks FlexRay needed for chassis networks and HSMv2 for secure boot | Choose only if migrating to next-gen architecture with PCIe backplane and accepting loss of FlexRay/HSMv2 compatibility |
Compared with MPC5746C-K100MJ6, SPC5746CK1AMMJ6 delivers extended temperature operation critical for direct engine-mounting; versus SPC5777MK1MMJ6, it retains FlexRay and HSMv2 essential for legacy chassis integration and secure OTA deployment-without over-provisioning unused compute resources.
Availability
SPC5746CK1AMMJ6 is available at Aetrix Electronics and suitable for engine control units, brake-by-wire systems, ADAS domain controllers, and vehicle gateways requiring stable component supply across automotive production lifecycles.
Supply support for SPC5746CK1AMMJ6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in functional safety and automotive-grade silicon.
The SPC5746CK1AMMJ6 belongs to NXP's SPC57 family of Power Architecture® microcontrollers designed specifically for ASIL-B-certified powertrain, chassis, and advanced driver assistance systems requiring deterministic real-time performance and hardware-enforced security.
FAQ
What is the maximum junction temperature specification for the SPC5746CK1AMMJ6?
The SPC5746CK1AMMJ6 is rated for a maximum junction temperature (TJ) of 150°C under bias, with ambient operating range from –40°C to +125°C. This rating is validated per AEC-Q100 Grade 0 qualification and enables direct mounting on high-temperature engine components. Thermal design must account for θJA of the 256-pin MAPBGA package on a 2s2p board layout.
Does the SPC5746CK1AMMJ6 support CAN FD in all eight FlexCAN modules?
Yes, the SPC5746CK1AMMJ6 supports CAN FD on all eight FlexCAN modules (FlexCAN0 through FlexCAN7), as confirmed in the MPC5746C datasheet Rev. 6 section "Family Comparison" and block diagram. Each channel operates up to 5 Mbps data phase and maintains full backward compatibility with classical CAN 2.0B.
Is the HSMv2 module in the SPC5746CK1AMMJ6 enabled by default?
No, the Hardware Security Module v2 (HSMv2) in the SPC5746CK1AMMJ6 is optional and requires explicit activation via fuse programming and PASS-based life-cycle state transition. Its presence is indicated by the "S" suffix in ordering codes (e.g., SPC5746CK1AMMJ6 includes HSMv2), but secure boot and cryptographic acceleration remain disabled until configured in production mode.
What external crystal frequencies are supported by the SPC5746CK1AMMJ6 clock system?
The SPC5746CK1AMMJ6 supports an 8–40 MHz external crystal on FXOSC_IN/OUT for primary clock generation, and a 32 kHz crystal on SXOSC_IN/OUT for RTC and low-power wake-up. The 16 MHz FIRC and 128 kHz SIRC internal RC oscillators provide fallback sources but are not crystal-based.
How many independent power supply domains does the SPC5746CK1AMMJ6 require?
The SPC5746CK1AMMJ6 requires four independent supply domains: three high-voltage I/O rails (VDD_HV_A, VDD_HV_B, VDD_HV_C) configurable at 3.3 V or 5 V, and one core logic rail (VDD_LV) at 1.2–1.32 V. VDD_HV_FLA is internally regulated and does not require a separate external supply when VDD_HV_A = 5 V.
SPC5746CK1AMMJ6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 256-LBGA
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 178
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5746CK1AMMJ6 FAQ
1.How can I place an order for SPC5746CK1AMMJ6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5746CK1AMMJ6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5746CK1AMMJ6 reliable?
The price and inventory of SPC5746CK1AMMJ6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5746CK1AMMJ6 is usually 5 days.
3.What payment methods are accepted for SPC5746CK1AMMJ6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5746CK1AMMJ6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5746CK1AMMJ6?
SPC5746CK1AMMJ6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5746CK1AMMJ6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5746CK1AMMJ6?
For technical support, including SPC5746CK1AMMJ6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5746CK1AMMJ6 requirements.
6.How does Aetrix verify that SPC5746CK1AMMJ6 is sourced from the original manufacturer or authorized distributors?
All SPC5746CK1AMMJ6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5746CK1AMMJ6 meets industry standards.
7.What is the process for return or replacement of SPC5746CK1AMMJ6?
All SPC5746CK1AMMJ6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5746CK1AMMJ6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5746CK1AMMJ6 part is unused and in its original packaging.
Return procedure for SPC5746CK1AMMJ6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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