NXP Semiconductors SPC5746CSK1AMMH6
- Part No.:
- SPC5746CSK1AMMH6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-LFBGA
- Datasheet:
-
SPC5746CSK1AMMH6.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 100MAPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SPC5746CSK1AMMH6 from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash, 384 KB SRAM with end-to-end ECC, and integrated FlexCAN FD (8 channels), Ethernet AVB/1588, Dual FlexRay, and HSMv2 security module. It targets ASIL-B safety-critical powertrain and chassis control units.
For engineers reviewing the SPC5746CSK1AMMH6 datasheet, SPC5746CSK1AMMH6 pinout, SPC5746CSK1AMMH6 application, or SPC5746CSK1AMMH6 equivalent, key selection criteria include dual-core deterministic timing, ISO 26262 ASIL-B compliance, hardware security for secure boot and key management, and support for high-bandwidth communication including 10/100 Ethernet with AVB and IEEE 1588 timestamping.
Technical Context
The SPC5746CSK1AMMH6 implements a crossbar switch architecture enabling concurrent access to flash, SRAM, and peripherals by multiple bus masters-including both e200z4 and e200z2 cores, eDMA, and debug interfaces. Its memory subsystem includes triple-ported 3 MB flash with three page buffers and 384 KB SRAM distributed across three RAM ports, all protected by SECDED ECC on 64-bit data + 29-bit address paths.
Timing and safety are enforced via a Clock Monitor Unit (CMU), Frequency Modulated PLL (FMPLL), Real-Time Counter (RTC), System Memory Protection Unit (SMPU) with 32 region descriptors, and Fault Collection and Control Unit (FCCU). The device supports functional safety up to ASIL-B per ISO 26262, with hardware-accelerated cryptography in HSMv2 and password-based device security (PASS).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160 MHz e200z4 + 80 MHz e200z2, both supporting VLE and single-precision floating-point |
| Flash Memory | 3 MB on-chip flash with ECC, triple-port controller, and Boot Assist Flash (BAF) for serial programming |
| SRAM | 384 KB on-chip SRAM across three ports, fully ECC-protected |
| Communication Interfaces | 8 × FlexCAN FD, 4 × DSPI, 4 × SPI, 16 × LINFlexD, 4 × I²C, 1 × ENET (10/100 MII/RMII with AVB & IEEE 1588), 2 × FlexRay |
| Analog Peripherals | Two ADCs (10-bit + 12-bit), three analog comparators, Cross Trigger Unit for synchronized sampling |
| Security & Safety | HSMv2 hardware security module, PASS lifecycle management, FCCU fault reporting, ISO 26262 ASIL-B certified functions |
| Package | 256-pin MAPBGA (MJ package code), 15 mm × 15 mm, 0.8 mm pitch |
Pinout & Package
SPC5746CSK1AMMH6 is housed in a 256-pin MAPBGA (package code MJ), 15 mm × 15 mm body size, 0.8 mm ball pitch, RoHS-compliant, with thermal pad exposed on underside for enhanced heat dissipation in automotive under-hood environments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / B / C | High-voltage I/O supply rails | Independent 3.3 V or 5 V supplies for I/O banks; enable mixed-voltage interface design and isolation of noise-sensitive domains |
| VDD_LV | Core logic supply | 1.2–1.32 V regulated core voltage; supports dynamic voltage scaling and low-power operation modes |
| VDD_HV_FLA | Flash supply input | 3.15–3.6 V dedicated flash regulator input; externally bypassed when VDD_HV_A = 3.3 V, internally regulated when VDD_HV_A = 5 V |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Supports 8–40 MHz external crystal; provides primary clock source for FMPLL and system timing stability |
| SXOSC_IN / SXOSC_OUT | 32 kHz real-time clock oscillator | Enables RTC operation and low-power wake-up during stop modes without main oscillator active |
| JTAG_TCK / TMS / TDI / TDO / TRST_B | Nexus Class 3+ debug interface | IEEE-ISTO 5001-2008 compliant; enables non-intrusive real-time tracing, breakpoint injection, and core-level debugging for both CPUs |
| FLEXCAN0_TX / RX through FLEXCAN7_TX / RX | CAN FD transceiver I/O | Eight independent CAN FD channels with configurable bit rates up to 5 Mbps; each pair supports loopback, self-test, and bus-off recovery |
| ENET_MDC / MDIO / TXD[0:3] / RXD[0:3] / CRS_DV / COL / REF_CLK | Ethernet physical layer interface | Full MII/RMII support with AVB time-synchronization and IEEE 1588 precision timestamping; enables deterministic networking in domain controllers |
Key Features
| Feature | Design Value |
|---|---|
| Dual e200z4/z2 CPU architecture | Enables partitioned real-time execution: z4 handles complex control algorithms and safety monitors; z2 manages communication stacks and diagnostics-reducing inter-core contention via crossbar arbitration |
| End-to-end ECC (SECDED) | Guarantees single-bit correction and double-bit detection across all bus transactions (cores, DMA, peripherals), eliminating silent data corruption in safety-critical memory accesses |
| HSMv2 + PASS security engine | Provides hardware-accelerated AES-128/256, SHA-256, RSA-2048, and secure key storage; supports secure boot, firmware authentication, and lifecycle state transitions (e.g., production → field update → decommission) |
| ASIL-B functional safety certification | Validated per ISO 26262 Part 5 & 6 for safety mechanisms including lockstep monitoring (where applicable), memory BIST, clock/fault monitoring, and SMPU-enforced memory isolation |
| Configurable I/O domains | Allows independent voltage assignment (3.3 V or 5 V) and pad keeper configuration per peripheral group (e.g., FlexCAN, LINFlexD, Ethernet), simplifying mixed-signal board integration |
| WKPU wake-up controller | Supports selective wake-up from deep-sleep modes via GPIO, CAN, LIN, or FlexRay events-enabling ultra-low-power vehicle network gateways with sub-100 µA standby current |
Applications
| Powertrain Control Unit (PCU) | Advanced Chassis Controller |
|---|---|
Use Scenario: Real-time combustion timing, fuel injection, and turbocharger actuation in gasoline/diesel engines with OBD-II diagnostics and torque coordination. IC Role / Device Role / Timing Role: Primary compute engine executing ASIL-B control loops at ≤1 ms cycle time; synchronizes ADC sampling, PWM generation, and CAN FD messaging via Cross Trigger Unit and eMIOS. Use Value: Dual-core deterministic scheduling ensures safety monitor (z2) runs independently of main control (z4); 3 MB flash accommodates dual-bank OTA updates without runtime interruption. |
Use Scenario: Integrated brake-by-wire, steering angle estimation, and suspension damping control requiring sensor fusion and fail-operational redundancy. IC Role / Device Role / Timing Role: Central safety controller managing CAN FD, FlexRay, and LIN networks; uses SMPU to isolate safety-critical tasks and FCCU to log transient faults for diagnostic traceability. Use Value: HSMv2 enables secure firmware signing and encrypted CAN FD message authentication; 384 KB ECC-SRAM guarantees integrity of real-time control variables across voltage transients. |
| Automotive Domain Gateway | Electric Vehicle Battery Management System (BMS) Master |
Use Scenario: High-speed bridging between CAN FD, Ethernet AVB, and LIN networks in zonal architectures, performing protocol translation and firewall filtering. IC Role / Device Role / Timing Role: Network convergence hub using ENET with IEEE 1588 timestamping to align event logs across domains; FlexCAN FD handles legacy ECU communication while Ethernet serves OTA and diagnostics. Use Value: Dual FlexRay channels provide deterministic backup communication path; 16-channel eDMA offloads packet routing from CPU, sustaining >200 Mbps aggregate throughput. |
Use Scenario: Central BMS controller aggregating cell voltage/temperature data from slave nodes, calculating SOC/SOH, and enforcing safety limits via contactor control and thermal management. IC Role / Device Role / Timing Role: Safety-certified master node executing ISO 26262-compliant battery algorithms; uses 12-bit ADC with programmable gain amplifiers for precise voltage measurement and CRC-protected SPI to daisy-chain slaves. Use Value: End-to-end ECC prevents corrupted cell data from triggering false overvoltage trips; PASS-enabled secure boot blocks unauthorized firmware that could compromise isolation barriers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5746CSDK1AMMH6 | Same die and feature set; differs only in qualification status (S = automotive qualified vs. P = engineering sample) and mask revision (K0 vs. K1) | Identical functional scope; used in pre-production validation where full AEC-Q100 qualification not yet required | Select SPC5746CSK1AMMH6 for production programs requiring full automotive qualification and long-term supply assurance. |
| SPC5777MK0MLU6 | Higher-performance variant: 300 MHz e200z7 core, 4 MB flash, 512 KB SRAM, additional FlexCAN FD and Ethernet queues; no HSMv2 (uses HSMv3) | Targets ASIL-D ADAS domain controllers and high-end gateway applications requiring greater compute headroom and expanded networking capacity | Choose SPC5777MK0MLU6 only when algorithm complexity or bandwidth demands exceed SPC5746CSK1AMMH6 capabilities; otherwise, SPC5746CSK1AMMH6 offers optimal cost/performance for ASIL-B systems. |
Compared with MPC5746CSDK1AMMH6, the SPC5746CSK1AMMH6 delivers identical functionality with full production qualification and documented lifecycle support; versus SPC5777MK0MLU6, it trades peak performance for lower power, smaller footprint, and proven ASIL-B certification-making it the preferred choice for cost-sensitive, thermally constrained powertrain and chassis modules.
Availability
SPC5746CSK1AMMH6 is available at Aetrix Electronics and suitable for automotive powertrain control, chassis electronics, and domain gateway applications requiring stable component supply, AEC-Q100 Grade 1 qualification, and long-term industrial availability.
Supply support for SPC5746CSK1AMMH6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in functional safety, security, and real-time processing.
The SPC5746CSK1AMMH6 belongs to NXP's SPC57 family of automotive MCUs, designed specifically for ASIL-B safety-critical applications in powertrain, chassis, and body control-emphasizing deterministic timing, hardware-enforced security, and robust mixed-signal integration.
FAQ
What is the operating temperature range for the SPC5746CSK1AMMH6?
The SPC5746CSK1AMMH6 is qualified for ambient temperatures from –40 °C to +125 °C (Grade 1), with junction temperature support up to +150 °C. This rating meets AEC-Q100 requirements for under-hood automotive applications, including engine control units and transmission control modules where thermal stress is significant. The device incorporates thermal monitoring circuitry and supports safe shutdown via FCCU-triggered interrupts if temperature thresholds are exceeded.
Does the SPC5746CSK1AMMH6 support CAN FD, and how many channels are available?
Yes, the SPC5746CSK1AMMH6 integrates eight independent FlexCAN3 modules, all supporting CAN FD with data rates up to 5 Mbps and flexible data payload lengths. Each channel operates autonomously with dedicated message RAM, interrupt vectors, and error counters-enabling simultaneous high-bandwidth communication with multiple ECUs in modern vehicle networks without CPU overhead.
How does the SPC5746CSK1AMMH6 implement functional safety per ISO 26262?
The SPC5746CSK1AMMH6 achieves ASIL-B compliance through hardware safety mechanisms including end-to-end ECC on all memory and bus paths, SMPU-enforced memory partitioning, FCCU fault collection, clock and voltage monitoring (CMU, LVD/HVD), and built-in self-test (MBIST) for memory arrays. These features are documented in NXP's ISO 26262 safety manual and supported by certified safety libraries for runtime diagnostics.
What debug interface does the SPC5746CSK1AMMH6 provide, and is it production-accessible?
The SPC5746CSK1AMMH6 features a Nexus Class 3+ debug interface compliant with IEEE-ISTO 5001-2008, accessible via JTAG/CJTAG pins. It supports real-time tracing, non-intrusive breakpoints, and core-level visibility for both e200z4 and e200z2 CPUs. Debug remains enabled in production parts but can be permanently disabled via fuse programming to prevent unauthorized access-ensuring security without sacrificing development flexibility.
Is the SPC5746CSK1AMMH6 pin-compatible with other members of the MPC5746C family?
No-pin compatibility is package-dependent. The SPC5746CSK1AMMH6 uses the 256-pin MAPBGA (MJ) package. While other MPC5746C variants like MPC5746CSK1AMMH3 use the same MJ package and share identical pinouts, variants in 176 LQFP-EP (KU) or 100 BGA (MH) packages have different pin counts and signal mappings. Always verify mechanical and electrical compatibility using the official NXP pinout diagram for SPC5746CSK1AMMH6 before PCB layout.
SPC5746CSK1AMMH6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-LFBGA
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- -
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5746CSK1AMMH6 FAQ
1.How can I place an order for SPC5746CSK1AMMH6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5746CSK1AMMH6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5746CSK1AMMH6 reliable?
The price and inventory of SPC5746CSK1AMMH6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5746CSK1AMMH6 is usually 5 days.
3.What payment methods are accepted for SPC5746CSK1AMMH6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5746CSK1AMMH6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5746CSK1AMMH6?
SPC5746CSK1AMMH6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5746CSK1AMMH6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5746CSK1AMMH6?
For technical support, including SPC5746CSK1AMMH6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5746CSK1AMMH6 requirements.
6.How does Aetrix verify that SPC5746CSK1AMMH6 is sourced from the original manufacturer or authorized distributors?
All SPC5746CSK1AMMH6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5746CSK1AMMH6 meets industry standards.
7.What is the process for return or replacement of SPC5746CSK1AMMH6?
All SPC5746CSK1AMMH6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5746CSK1AMMH6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5746CSK1AMMH6 part is unused and in its original packaging.
Return procedure for SPC5746CSK1AMMH6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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