NXP Semiconductors SPC5746CSK1MKU6R
- Part No.:
- SPC5746CSK1MKU6R
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 176-LQFP Exposed Pad
- Datasheet:
-
SPC5746CSK1MKU6R.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,989
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SPC5746CSK1MKU6R from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash, 384 KB SRAM with end-to-end ECC, and integrated HSMv2 security module. It supports CAN FD (8 FlexCAN channels), Ethernet AVB/1588, FlexRay, and ISO 26262 ASIL-B functional safety - deployed in engine control units and advanced driver assistance systems.
For engineers reviewing the SPC5746CSK1MKU6R datasheet, SPC5746CSK1MKU6R pinout, SPC5746CSK1MKU6R application, or SPC5746CSK1MKU6R equivalent, this page delivers verified technical context, validated pin assignments for the 176-pin LQFP-EP package, real-world automotive use cases, and two confirmed alternative parts with documented functional and packaging differences.
Technical Context
The SPC5746CSK1MKU6R implements a tightly coupled dual-core architecture where the e200z4 core handles high-intensity real-time tasks (e.g., torque calculation) and the e200z2 core manages background services (e.g., diagnostics, communication stack). Both cores share a crossbar switch and SMPU with 32 region descriptors for memory protection.
Its clock system integrates FMPLL, 8–40 MHz FXOSC, 32 kHz SXOSC, and 16 MHz FIRC to support dynamic frequency scaling across operating modes. All bus masters generate SECDED codes covering 64-bit data + 29-bit address, ensuring full ECC coverage for flash, SRAM, and peripheral registers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160 MHz e200z4 + 80 MHz e200z2, both supporting VLE for code density reduction |
| Flash Memory | 3 MB on-chip flash with triple-port controller, EEE emulation, and RWW capability |
| SRAM | 384 KB distributed across three RAM ports, all protected by end-to-end ECC |
| Functional Safety | ISO 26262 ASIL-B certified; includes FCCU fault collection, STM watchdog timers, and SMPU memory isolation |
| Communication Interfaces | 8 FlexCAN3 modules with CAN FD, 4 DSPI, 4 SPI, 16 LINFlexD, 4 I²C, ENET (MII/RMII + IEEE 1588 + AVB), dual-channel FlexRay |
| Analog Peripherals | One 10-bit ADC (68 ch), one 12-bit ADC (31 ch), three analog comparators, and Cross Trigger Unit for synchronized sampling |
| Security | HSMv2 hardware security module with PASS lifecycle management and secure boot via Boot Assist Flash (BAF) |
Pinout & Package
SPC5746CSK1MKU6R is housed in a 176-pin LQFP-EP (exposed pad) package, RoHS-compliant, with 0.5 mm pitch and 24 × 24 mm body size. Pin assignments follow NXP's standardized SIUL2 multiplexing scheme, supporting configurable I/O domains for CAN, LIN, Ethernet, and general-purpose functions.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / VDD_HV_B / VDD_HV_C | High-voltage I/O supply rails | Independent 3.3 V or 5 V supplies for I/O banks; VDD_HV_B and VDD_HV_C are internally tied on this LQFP variant |
| VDD_LV | Core logic supply | 1.2–1.32 V supply for e200z4/z2 cores and internal logic; requires external decoupling per Table 9 |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Supports 8–40 MHz external crystal; essential for FMPLL reference and system clock generation |
| SXOSC_IN / SXOSC_OUT | 32 kHz real-time clock oscillator | Enables RTC operation and low-power wake-up without main crystal active |
| RESET_B | Active-low reset input | Asynchronous reset pin with internal pull-up; triggers PORST sequence and BAF execution if asserted during power-up |
| JTAG_TCK / JTAG_TMS / JTAG_TDI / JTAG_TDO / JTAG_TRST_B | Nexus Class 3+ debug interface | IEEE-ISTO 5001-2008 compliant; enables real-time trace, core halt, and memory access for both e200z4 and e200z2 |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core deterministic execution | e200z4 (160 MHz) + e200z2 (80 MHz) with shared crossbar and independent INTC routing - enables lockstep-free safety partitioning |
| End-to-end ECC protection | SECDED applied to all bus transactions (flash, SRAM, peripherals); covers 64-bit data + 29-bit address for full memory path integrity |
| Automotive-grade communication suite | 8 FlexCAN FD channels, dual FlexRay, ENET with AVB/1588, and 16 LINFlexD - meets requirements for domain controllers and gateway ECUs |
| Hardware Security Module v2 | HSMv2 with AES-128/256, SHA-256, RSA-2048, secure key storage, and PASS-based device lifecycle enforcement |
| Configurable low-power operation | WKPU-controlled wake-up from STOP/STANDBY modes via CAN, LIN, FlexRay, or GPIO; supports <10 µA deep-sleep current |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance System (ADAS) Domain Controller |
|---|---|
Use Scenario: Real-time combustion timing, fuel injection, and exhaust gas recirculation control in gasoline/diesel powertrains. IC Role / Device Role / Timing Role: Primary compute engine executing ASIL-B safety-critical control loops with deterministic latency under 50 µs. Use Value: Dual-core separation allows z4 to run PID control at 160 MHz while z2 handles CAN FD diagnostics and firmware updates without jitter. |
Use Scenario: Sensor fusion hub aggregating radar, camera, and ultrasonic inputs for AEB and lane-keeping functions. IC Role / Device Role / Timing Role: Central domain controller managing time-synchronized data ingestion via FlexRay and Ethernet AVB streams. Use Value: Integrated 1588 PTP hardware and multi-queue ENET enable sub-microsecond timestamp alignment across heterogeneous sensor interfaces. |
| Electric Vehicle (EV) Battery Management System (BMS) | Automotive Gateway ECU |
Use Scenario: Cell voltage monitoring, thermal management, and SOC/SOH estimation in high-voltage traction battery packs. IC Role / Device Role / Timing Role: Safety-certified host processor interfacing with isolated ADCs and communicating over CAN FD to cell controllers. Use Value: On-chip 12-bit ADC with cross-trigger unit synchronizes sampling across 31 channels using eMIOS timer events - eliminating external trigger wiring. |
Use Scenario: Protocol translation and firewall between vehicle backbone (CAN FD/FlexRay) and infotainment domain (Ethernet). IC Role / Device Role / Timing Role: Secure gateway enforcing message filtering, intrusion detection, and OTA update validation via HSMv2. Use Value: Hardware-accelerated crypto and PASS-based secure boot ensure only signed, versioned firmware executes - preventing unauthorized reprogramming. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5748G | Same dual-core e200z4/z2 architecture but adds 2 MB HSM code space and 16 KB HSM data flash; no FlexRay; 256/324 BGA only | Targeted at HSM-heavy applications (e.g., secure telematics) where FlexRay is unnecessary and larger package is acceptable | Select MPC5748G only when HSM code footprint exceeds SPC5746CSK1MKU6R's 64 KB and FlexRay is not required |
| SPC58NG84S2 | Tri-core (e200z7 + dual e200z4), 8 MB flash, 2 MB SRAM, supports ASIL-D; 256 BGA only; no FlexRay; higher power envelope | Used in central vehicle computers requiring higher compute throughput and ASIL-D decomposition - not drop-in compatible | Choose SPC58NG84S2 for next-gen zonal architectures needing >160 MHz sustained performance and formal ASIL-D certification |
Compared with MPC5746CSK1MKU6R, MPC5748G trades FlexRay for expanded HSM resources and lacks LQFP packaging, while SPC58NG84S2 delivers tri-core scalability and ASIL-D readiness at the cost of power, package size, and legacy interface support - making SPC5746CSK1MKU6R optimal for cost-sensitive, FlexRay-dependent ASIL-B ECUs in LQFP form factor.
Availability
SPC5746CSK1MKU6R is available at Aetrix Electronics and suitable for engine control units, ADAS domain controllers, EV battery management systems, and automotive gateway ECUs requiring stable component supply across extended automotive lifecycles.
Supply support for SPC5746CSK1MKU6R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in Power Architecture® and functional safety.
The SPC5746CSK1MKU6R belongs to NXP's SPC57 family of automotive MCUs, designed specifically for ASIL-B real-time control in powertrain, chassis, and safety-critical body electronics - emphasizing dual-core determinism, end-to-end ECC, and integrated HSMv2.
FAQ
What is the maximum operating temperature range for the SPC5746CSK1MKU6R?
The SPC5746CSK1MKU6R is qualified for ambient temperatures from –40 °C to +125 °C (Ta), with junction temperature rated up to +150 °C. This rating applies under specified voltage conditions (e.g., VDD_HV = 3.3 V or 5 V) and is validated per NXP's Rev. 6 datasheet. The SPC5746CSK1MKU6R maintains full ASIL-B functionality across this range when used with appropriate thermal design and decoupling.
Does the SPC5746CSK1MKU6R support CAN FD, and how many channels are available?
Yes, the SPC5746CSK1MKU6R supports CAN FD on all eight FlexCAN3 modules (FlexCAN0 through FlexCAN7), each capable of bit rates up to 5 Mbps in FD mode. This capability is confirmed in the Family Comparison table and peripheral operating requirements section of the official datasheet. The SPC5746CSK1MKU6R uses dedicated CAN FD transceivers and supports protocol arbitration, payload length extension, and flexible data rate switching without software overhead.
What package type and pin count does the SPC5746CSK1MKU6R use?
The SPC5746CSK1MKU6R uses a 176-pin LQFP-EP (leadless quad flat package with exposed pad) with 0.5 mm pitch and 24 mm × 24 mm body size. This package is explicitly listed in Table 1 (Family Comparison) and Section 8 (Dimensions) of the MPC5746C datasheet. The SPC5746CSK1MKU6R's KU suffix in the part number directly denotes the 176 LQFP-EP variant, distinguishing it from BGA options (MJ/MN/MH).
Is the SPC5746CSK1MKU6R ISO 26262 ASIL-B certified, and what safety mechanisms does it include?
Yes, the SPC5746CSK1MKU6R is ISO 26262 ASIL-B certified for specific safety-related functions including CPU lockstep alternatives, memory protection, and fault handling. It includes SMPU with 32 region descriptors, FCCU for fault collection, dual SWT and STM watchdogs, and end-to-end ECC across flash, SRAM, and buses. These mechanisms are documented in the Functional Safety section of the datasheet and validated in NXP's safety manual. The SPC5746CSK1MKU6R does not support full ASIL-D decomposition.
What debug interface does the SPC5746CSK1MKU6R support, and is Nexus Class 3+ available on this package?
The SPC5746CSK1MKU6R supports IEEE-ISTO 5001-2008 Nexus Class 3+ debug via its JTAG interface (TCK/TMS/TDI/TDO/TRST_B pins), enabling real-time trace, instruction-level debugging, and memory access for both e200z4 and e200z2 cores. While Nexus Class 3+ is implemented, the 176 LQFP-EP package does not expose the full 32-bit trace port - trace bandwidth is limited to 4-bit parallel output. This configuration is confirmed in Section 6.5 (Debug specifications) and Table 1 of the datasheet. The SPC5746CSK1MKU6R supports NDI-compliant tools such as Lauterbach TRACE32.
SPC5746CSK1MKU6R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 176-LQFP Exposed Pad
- Series:
- MPC57xx
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 129
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5746CSK1MKU6R FAQ
1.How can I place an order for SPC5746CSK1MKU6R through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5746CSK1MKU6R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5746CSK1MKU6R reliable?
The price and inventory of SPC5746CSK1MKU6R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5746CSK1MKU6R is usually 5 days.
3.What payment methods are accepted for SPC5746CSK1MKU6R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5746CSK1MKU6R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5746CSK1MKU6R?
SPC5746CSK1MKU6R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5746CSK1MKU6R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5746CSK1MKU6R?
For technical support, including SPC5746CSK1MKU6R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5746CSK1MKU6R requirements.
6.How does Aetrix verify that SPC5746CSK1MKU6R is sourced from the original manufacturer or authorized distributors?
All SPC5746CSK1MKU6R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5746CSK1MKU6R meets industry standards.
7.What is the process for return or replacement of SPC5746CSK1MKU6R?
All SPC5746CSK1MKU6R units undergo pre-shipment inspection (PSI). If there is an issue with SPC5746CSK1MKU6R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5746CSK1MKU6R part is unused and in its original packaging.
Return procedure for SPC5746CSK1MKU6R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SPC5746CSK1MKU6R Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

