NXP Semiconductors SPC5747CBK0ACKU6
- Part No.:
- SPC5747CBK0ACKU6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 176-LQFP Exposed Pad
- Datasheet:
-
SPC5747CBK0ACKU6.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,071
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SPC5747CBK0ACKU6 from NXP Semiconductors is an automotive-qualified Power Architecture® 32-bit microcontroller featuring dual e200z4 cores (160 MHz) and one e200z2 core (80 MHz), 4 MB on-chip flash, 512 KB SRAM with end-to-end ECC, and integrated safety features compliant with ISO 26262 ASIL-B for body control applications. It supports CAN FD, LIN, FlexRay, Ethernet, and hardware security module (HSMv2) for secure boot and life-cycle management.
For engineers reviewing the SPC5747CBK0ACKU6 datasheet, SPC5747CBK0ACKU6 pinout, SPC5747CBK0ACKU6 application, or SPC5747CBK0ACKU6 equivalent, this page delivers verified technical context, validated pin assignments for the 176-pin LQFP-EP package, functional safety architecture details, and confirmed alternative parts for body control module (BCM) and gateway designs requiring deterministic real-time performance and ASIL-B certification.
Technical Context
The SPC5747CBK0ACKU6 implements a tri-core architecture with two high-performance e200z4 CPUs (160 MHz, VLE support, single-precision FPU, 8 KB I-cache/4 KB D-cache) and one e200z2 CPU (80 MHz, VLE-only), all sharing memory coherency via a multi-port crossbar switch. End-to-end ECC secures all bus transactions across 64-bit data and 29-bit address paths, covering flash, SRAM, and peripheral interfaces.
It integrates dual SMPUs (12-region each), 16 semaphores, and a 32-channel eDMA controller with DMAMUX routing. Clocking includes FMPLL, 8–40 MHz FXOSC, 32 kHz SXOSC, 16 MHz FIRC, and 128 kHz SIRC, enabling flexible low-power operation with WKPU wake-up support and multiple sleep modes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Configuration | Two e200z4 @ 160 MHz + one e200z2 @ 80 MHz; enables parallel real-time task partitioning across safety-critical and non-safety domains. |
| Flash Memory | 4 MB on-chip flash with triple-port controller and EEE emulation; supports in-field reprogramming via BAF over LIN/SCI. |
| SRAM | 512 KB on-chip SRAM with ECC protection; split across three RAM ports for concurrent access by CPU, DMA, and peripherals. |
| Functional Safety | ISO 26262 ASIL-B certified; includes FCCU fault collection, HSMv2 for secure boot, and dual SMPUs for memory isolation. |
| Communication Interfaces | 8 FlexCAN modules (all with optional CAN FD), 18 LINFlexD, 4 DSPI, 6 SPI, 4 I²C, 2x 10-/12-bit ADCs, and 96 eMIOS channels. |
| Package | 176-pin LQFP-EP (KU); exposes full I/O set including dedicated CAN/LIN/Ethernet pins and configurable voltage domains. |
| Operating Temperature | –40 °C to +125 °C ambient; qualified for under-hood automotive environments per AEC-Q100 Grade 0. |
Pinout & Package
SPC5747CBK0ACKU6 is housed in a 176-pin LQFP-EP (exposed pad) package with 0.5 mm pitch, optimized for thermal dissipation and automotive PCB layout. Pin assignments follow NXP's standardized MPC574xC pinout family, with dedicated power domains (VDD_HV_A/B/C, VDD_LV), clock inputs (FXOSC, SXOSC), and peripheral-specific signal groups (CAN0–CAN7, LIN0–LIN17, ETH0/ETH1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A | High-voltage I/O supply | 3.3 V or 5.0 V main I/O rail; powers GPIO, CAN transceivers, LIN drivers, and ADC reference circuitry. |
| VDD_LV | Core logic supply | 1.2–1.32 V regulated core voltage; feeds e200z4/z2 CPUs, caches, and internal buses with LVD/HVD monitoring. |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Connects 8–40 MHz external crystal; provides primary clock source for FMPLL and system timing. |
| CAN0_TX / CAN0_RX | FlexCAN0 differential pair | Direct connection to external CAN transceiver; supports CAN FD up to 5 Mbps with programmable bit timing. |
| LIN0_TX / LIN0_RX | LINFlexD0 serial interface | Single-wire UART-compatible bus; enables body control communication at up to 20 kbps with auto-baud detection. |
| ETH0_MDC / ETH0_MDIO | IEEE 802.3 MII management interface | Configures ENET complex registers; required for PHY initialization and link status monitoring in 10/100 Ethernet mode. |
Key Features
| Feature | Design Value |
|---|---|
| Dual e200z4 Core Architecture | Enables lockstep or split-mode execution for ASIL-B decomposition; supports time-triggered scheduling with PIT/STM timers. |
| End-to-End ECC Protection | SECDED coverage across flash, SRAM, and bus interconnects ensures data integrity without software overhead or latency penalty. |
| HSMv2 Security Module | Hardware-accelerated AES-128/256, SHA-256, and RSA-2048; supports secure boot, key provisioning, and firmware authentication. |
| Configurable I/O Voltage Domains | Independent 3.3 V/5.0 V domains for CAN, LIN, Ethernet, USB, and general-purpose I/O simplify mixed-voltage board design. |
| Boot Assist Flash (BAF) | Enables field firmware updates via LIN or SCI without external debugger; supports encrypted image loading and signature verification. |
Applications
| Body Control Module (BCM) | Powertrain Gateway |
|---|---|
Use Scenario: Centralized vehicle body electronics managing lighting, door locks, window lifts, and climate control via LIN/CAN networks. IC Role / Device Role / Timing Role: Primary MCU executing real-time control tasks, coordinating LIN slaves, and routing CAN messages between chassis and infotainment domains. Use Value: 4 MB flash stores multiple firmware variants; ASIL-B compliance meets OEM functional safety requirements for Class C systems. | Use Scenario: Aggregating and translating signals between engine control unit (ECU), transmission, and ADAS domain controllers using CAN FD and FlexRay. IC Role / Device Role / Timing Role: Gateway processor performing protocol conversion, message filtering, and secure firmware update distribution across heterogeneous automotive networks. Use Value: Dual Ethernet interfaces enable OTA update delivery; HSMv2 ensures cryptographic integrity of downloaded images. |
| Chassis Domain Controller | Electric Vehicle (EV) Battery Management Interface |
Use Scenario: Coordinating ABS, ESC, and steering assist functions with deterministic response to sensor inputs and actuator commands. IC Role / Device Role / Timing Role: Safety-certified host controller interfacing with analog sensors (wheel speed, pressure), PWM actuators, and CAN-based brake modules. Use Value: 96 eMIOS channels provide precise PWM generation and input capture; SMPU enforces strict memory partitioning between safety and non-safety code. | Use Scenario: Monitoring cell voltages, temperatures, and pack current in high-voltage battery systems using isolated ADCs and CAN FD telemetry. IC Role / Device Role / Timing Role: BMS interface MCU acquiring analog measurements via 10-/12-bit ADCs and transmitting diagnostic data over CAN FD to central vehicle controller. Use Value: 512 KB ECC SRAM buffers sensor logs; WKPU enables ultra-low-power wake-on-event for cell imbalance alerts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5748GK0ACKU6 | 6 MB flash, 768 KB SRAM, adds third e200z4 core and HSMv2 as standard; higher pin count (256 BGA) and extended peripheral set. | Targeted at gateway and ADAS fusion applications requiring larger code footprint and dual Ethernet switching. | Select when >4 MB flash, >512 KB SRAM, or dual ENET L2 switch functionality is required; not drop-in compatible due to package and pinout differences. |
| SPC5746CK0ACKU6 | 3 MB flash, 512 KB SRAM, single e200z4 + e200z2; omits FlexRay, second Ethernet, and some CAN FD channels. | Suitable for cost-sensitive body control modules where reduced peripheral count lowers BOM and layout complexity. | Valid alternative for BCM designs without FlexRay or dual Ethernet needs; shares same 176 LQFP-EP package and pinout for mechanical compatibility. |
Compared with SPC5747CBK0ACKU6, MPC5748GK0ACKU6 offers greater memory and networking capability at the cost of package migration, while SPC5746CK0ACKU6 reduces feature set and cost but retains mechanical fit-enabling scalable platform design across vehicle tiers.
Availability
SPC5747CBK0ACKU6 is available at Aetrix Electronics and suitable for automotive body control modules, powertrain gateways, chassis domain controllers, and EV battery management interfaces requiring stable component supply, long-term lifecycle support, and AEC-Q100 qualification.
Supply support for SPC5747CBK0ACKU6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The SPC5747CBK0ACKU6 belongs to NXP's SPC574xC automotive microcontroller family, designed specifically for ASIL-B-compliant body electronics and gateway applications demanding high integration, functional safety, and secure firmware execution.
FAQ
What is the maximum operating frequency of the SPC5747CBK0ACKU6 CPU cores?
The SPC5747CBK0ACKU6 features two e200z4 cores operating at up to 160 MHz and one e200z2 core at up to 80 MHz. These frequencies are guaranteed across the full –40 °C to +125 °C ambient temperature range under specified voltage conditions (VDD_LV = 1.2–1.32 V, VDD_HV = 3.3 V or 5.0 V). The e200z4 cores include VLE encoding and single-precision floating-point units, while the e200z2 supports VLE only for compact code footprint.
Does the SPC5747CBK0ACKU6 support CAN FD, and how many channels are available?
Yes, the SPC5747CBK0ACKU6 supports CAN FD on all eight integrated FlexCAN modules. Each channel is independently configurable for classic CAN or CAN FD operation up to 5 Mbps, with programmable bit timing, flexible data-length control, and built-in CRC protection. CAN FD capability is enabled by default and does not require optional configuration bits or external components.
What safety certifications apply to the SPC5747CBK0ACKU6?
The SPC5747CBK0ACKU6 is ISO 26262 ASIL-B certified for functional safety, with supporting documentation including FMEDA reports, safety manuals, and diagnostic coverage analysis. It integrates hardware safety mechanisms such as FCCU for fault collection, dual SMPUs for memory isolation, end-to-end ECC, and lockstep-capable CPU configurations. These features are validated per ISO 26262 Part 5 and Part 6 for use in automotive body control and gateway systems.
What package type and pin count does the SPC5747CBK0ACKU6 use?
The SPC5747CBK0ACKU6 uses a 176-pin LQFP-EP (leadless quad flat package with exposed pad) package, designated by the suffix "KU" in its part number. This package has 0.5 mm pitch, measures 24 mm × 24 mm, and includes an exposed thermal pad for enhanced heat dissipation. All pin assignments-including power, clock, CAN, LIN, Ethernet, and GPIO-are fully documented in NXP's MPC574xC Pinout Reference Manual Rev. 4.
How much on-chip flash and SRAM does the SPC5747CBK0ACKU6 include?
The SPC5747CBK0ACKU6 includes 4 MB of on-chip flash memory with triple-port controller and EEPROM emulation (EEE) support, plus 512 KB of on-chip SRAM distributed across three independent ports. Both memory types implement end-to-end ECC protection for single-error correction and double-error detection. Flash supports background read-while-write (RWW) operations, and SRAM is partitioned to allow concurrent access by CPU, DMA, and peripherals without arbitration delay.
SPC5747CBK0ACKU6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 176-LQFP Exposed Pad
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz, 160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 129
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 3.15V ~ 5.5V
- Data Converters:
- A/D 48x10b, 16x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5747CBK0ACKU6 FAQ
1.How can I place an order for SPC5747CBK0ACKU6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5747CBK0ACKU6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5747CBK0ACKU6 reliable?
The price and inventory of SPC5747CBK0ACKU6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5747CBK0ACKU6 is usually 5 days.
3.What payment methods are accepted for SPC5747CBK0ACKU6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5747CBK0ACKU6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5747CBK0ACKU6?
SPC5747CBK0ACKU6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5747CBK0ACKU6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5747CBK0ACKU6?
For technical support, including SPC5747CBK0ACKU6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5747CBK0ACKU6 requirements.
6.How does Aetrix verify that SPC5747CBK0ACKU6 is sourced from the original manufacturer or authorized distributors?
All SPC5747CBK0ACKU6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5747CBK0ACKU6 meets industry standards.
7.What is the process for return or replacement of SPC5747CBK0ACKU6?
All SPC5747CBK0ACKU6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5747CBK0ACKU6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5747CBK0ACKU6 part is unused and in its original packaging.
Return procedure for SPC5747CBK0ACKU6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SPC5747CBK0ACKU6 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

