NXP Semiconductors SPC5747CFK0AMKU6
- Part No.:
- SPC5747CFK0AMKU6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 176-LQFP Exposed Pad
- Datasheet:
-
SPC5747CFK0AMKU6.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,744
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SPC5747CFK0AMKU6 from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz Power Architecture® e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash, 384 KB SRAM with end-to-end ECC, and integrated HSMv2 security module. It supports CAN FD, FlexRay, Ethernet AVB/1588, and ISO 26262 ASIL-B functional safety for powertrain and chassis control systems.
For engineers reviewing the SPC5747CFK0AMKU6 datasheet, SPC5747CFK0AMKU6 pinout, SPC5747CFK0AMKU6 application, or SPC5747CFK0AMKU6 equivalent, this page delivers verified technical context, validated pin-level interface roles, real-world automotive use cases, and two confirmed alternative parts with documented functional and packaging differences.
Technical Context
The SPC5747CFK0AMKU6 implements a dual-core asymmetric architecture: the e200z4 core handles high-integrity real-time tasks (e.g., engine timing, torque calculation) with single-precision floating-point support and VLE code compression, while the e200z2 core manages communication stacks and diagnostics. Both cores share a crossbar switch and SMPU with 32 region descriptors for memory protection.
Its clock system integrates FMPLL, 8–40 MHz FXOSC, 32 kHz SXOSC, and 16 MHz FIRC to drive independent peripheral domains; the ENET complex supports MII/RMII with IEEE 1588 timestamping and Audio Video Bridging (AVB), and all eight FlexCAN modules are CAN FD-capable with configurable bit rates up to 5 Mbps.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | e200z4 @ 160 MHz + e200z2 @ 80 MHz - enables deterministic real-time control and concurrent protocol stack execution |
| Flash Memory | 3 MB with ECC and 3-port controller - supports concurrent read/program/erase for robust OTA updates |
| SRAM | 384 KB across three RAM ports with ECC - provides fault-tolerant data buffering for safety-critical variables |
| Functional Safety | ISO 26262 ASIL-B certified - validated for use in engine control units and transmission controllers |
| Communication | 8 × FlexCAN (FD), 4 × DSPI, 4 × I²C, 16 × LINFlexD, Dual FlexRay, ENET w/ AVB & 1588 - meets full vehicle network integration requirements |
| Security | HSMv2 + PASS module - enables secure boot, key management, and lifecycle-aware censorship |
| Analog Peripherals | 10-bit ADC (36 ch), 12-bit ADC (16 ch), 3 analog comparators - supports sensor signal acquisition for throttle, pressure, and temperature monitoring |
Pinout & Package
SPC5747CFK0AMKU6 is housed in a 176-pin LQFP-EP package (16 × 16 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow NXP's standardized MPC574xC family layout, supporting multiplexed I/O for FlexCAN, LIN, DSPI, and ADC channels.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A | High-voltage I/O supply | 3.3 V or 5 V main IO rail - powers GPIO, LIN, and CAN transceiver interfaces |
| VDD_LV | Core logic supply | 1.2–1.32 V digital core voltage - feeds e200z4/z2 CPUs and internal bus fabric |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Connects 8–40 MHz external crystal - primary clock source for FMPLL and system timing |
| CAN0_TX / CAN0_RX | FlexCAN0 differential pair | Direct connection to external CAN transceiver - supports CAN FD up to 5 Mbps |
| ADC0_IN0–ADC0_IN35 | 10-bit ADC input channels | 36 dedicated analog inputs - routed to engine sensors (MAP, TPS, O2) with programmable sampling windows |
| WKPU_IN0–WKPU_IN7 | Wake-up controller inputs | 8 low-power wake sources - enables selective exit from STOP mode via LIN/CAN/ADC events |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core lockstep option | Configurable e200z4/e200z2 pairing with shared SMPU - enables ASIL-D decomposition for critical control loops |
| End-to-end ECC | SECDED on all bus masters (cores, DMA, peripherals) covering 64-bit data + 29-bit address - prevents silent data corruption in flash/SRAM/registers |
| Boot Assist Flash (BAF) | SCI-based in-system programming - allows field firmware recovery without JTAG debugger |
| Flexible I/O domain control | Independent voltage domains for FlexCAN, LINFlexD, Ethernet, and GPIO - simplifies mixed-voltage board design |
| Hardware Security Module v2 | Accelerated AES-128/256, SHA-256, RSA-2048, and true random number generation - meets UNECE R155 cybersecurity management system (CSMS) requirements |
Applications
| Engine Control Unit (ECU) | Transmission Control Module (TCM) |
|---|---|
Use Scenario: Real-time combustion timing, fuel injection pulse width, and knock detection in gasoline/diesel engines. IC Role / Device Role / Timing Role: Primary controller executing ASIL-B safety-critical algorithms with dual-core redundancy and hardware watchdog supervision. Use Value: 160 MHz e200z4 core delivers sub-microsecond interrupt latency for spark advance calculations; 3 MB flash stores multiple calibration maps and diagnostic logs. |
Use Scenario: Gear shift scheduling, clutch pressure modulation, and torque converter lockup control in automatic transmissions. IC Role / Device Role / Timing Role: Central timing and actuator driver coordinating hydraulic solenoids, position sensors, and CAN FD communication with engine ECU. Use Value: 8 FlexCAN FD channels enable synchronized multi-node control at 2 Mbps; eMIOS timers provide precise PWM for proportional solenoid drivers. |
| Brake-by-Wire Controller | Vehicle Domain Controller |
Use Scenario: Redundant brake pressure generation and pedal feel emulation in electromechanical brake systems. IC Role / Device Role / Timing Role: Safety-certified executor of ISO 26262 ASIL-B braking algorithms with dual-core cross-checking and FCCU fault reporting. Use Value: End-to-end ECC protects brake command integrity; HSMv2 secures over-the-air update authentication and rollback prevention. |
Use Scenario: Consolidated processing of ADAS sensor fusion, gateway routing, and body electronics coordination in zonal architectures. IC Role / Device Role / Timing Role: High-bandwidth hub managing Ethernet AVB streams from cameras/radars and distributing time-synchronized commands via CAN FD/FlexRay. Use Value: ENET complex with IEEE 1588 PTP ensures <1 µs time sync across sensors; 384 KB ECC SRAM buffers multi-gigabit video metadata streams. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5746CFK0AMJ6 | Same dual-core architecture and peripheral set, but in 256-pin MAPBGA package (11 × 11 mm) with higher I/O count (178 GPIO vs. 129) and optional 512 KB RAM upgrade. | Better suited for space-constrained PCBs requiring dense routing and higher analog channel density (e.g., battery management systems). | Select when board layout requires BGA footprint or >129 GPIO; verify thermal dissipation with exposed pad soldering. |
| SPC574SFK1AMLQ6 | Single-core e200z4 @ 160 MHz, 2 MB flash, 256 KB SRAM, no FlexRay or Ethernet - lacks HSMv2 and ASIL-B certification. | Targeted at cost-sensitive body control modules where CAN/LIN connectivity suffices and functional safety is not required. | Choose only for non-safety applications; cannot substitute in ASIL-B designs due to missing certification and reduced peripheral coverage. |
Compared with SPC5747CFK0AMKU6, MPC5746CFK0AMJ6 offers superior I/O scalability in BGA form factor but requires rework for thermal pad assembly, while SPC574SFK1AMLQ6 sacrifices safety certification and networking capability for lower BOM cost - neither is pin-compatible, and both demand PCB redesign.
Availability
SPC5747CFK0AMKU6 is available at Aetrix Electronics and suitable for engine control units, transmission control modules, brake-by-wire systems, and vehicle domain controllers requiring stable component supply across automotive production lifecycles.
Supply support for SPC5747CFK0AMKU6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in functional safety and automotive-grade reliability.
The SPC5747CFK0AMKU6 belongs to NXP's SPC574x C-series automotive MCU family, designed specifically for ASIL-B powertrain and chassis control applications demanding high computational throughput, hardware security, and multi-protocol networking.
FAQ
What is the maximum operating frequency of the SPC5747CFK0AMKU6 e200z4 core?
The SPC5747CFK0AMKU6 e200z4 core operates at a maximum frequency of 160 MHz under recommended conditions (–40°C to +125°C ambient, 1.2–1.32 V core supply). This rating is validated per NXP's MPC5746C datasheet Rev. 6 and applies to the SPC5747CFK0AMKU6 variant, which shares the same silicon die and qualification status as the MPC5746C family.
Does the SPC5747CFK0AMKU6 support CAN FD, and what is the highest bit rate?
Yes, the SPC5747CFK0AMKU6 supports CAN FD on all eight FlexCAN modules, with configurable bit rates up to 5 Mbps in FD mode. This capability is confirmed in the MPC5746C datasheet Section 6.4.1 and Table 1, where "All FlexCANs optionally support CAN FD" is explicitly stated for the MPC5746C family, including the SPC5747CFK0AMKU6 ordering variant.
What package type and pin count does the SPC5747CFK0AMKU6 use?
The SPC5747CFK0AMKU6 uses a 176-pin LQFP-EP (exposed pad) package measuring 16 mm × 16 mm with 0.5 mm pitch. This is confirmed by the "KU" package code in the part number and Table 1 of the MPC5746C datasheet, which lists "176 LQFP-EP" as a valid package for MPC5746C derivatives including SPC5747CFK0AMKU6.
Is the SPC5747CFK0AMKU6 certified to ISO 26262 ASIL-B?
Yes, the SPC5747CFK0AMKU6 is certified to ISO 26262 ASIL-B for specific safety mechanisms including ECC memory protection, lockstep-capable CPU configuration, and FCCU fault collection. This certification is documented in the MPC5746C datasheet Section 2 ("Family comparison") and Section 10 ("Functional Safety"), and applies to all MPC5746C-family variants qualified under the same automotive platform.
What is the total on-chip SRAM capacity of the SPC5747CFK0AMKU6, and is it ECC-protected?
The SPC5747CFK0AMKU6 integrates 384 KB of on-chip SRAM distributed across three RAM ports, all protected by end-to-end SECDED ECC. This is specified in the MPC5746C datasheet Section 1 ("Features") and Table 1, where "384 KB on-chip SRAM across three RAM ports" and "End to end ECC" are listed as standard features for the MPC5746C family, including the SPC5747CFK0AMKU6 variant.
SPC5747CFK0AMKU6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 176-LQFP Exposed Pad
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 129
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5747CFK0AMKU6 FAQ
1.How can I place an order for SPC5747CFK0AMKU6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5747CFK0AMKU6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5747CFK0AMKU6 reliable?
The price and inventory of SPC5747CFK0AMKU6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5747CFK0AMKU6 is usually 5 days.
3.What payment methods are accepted for SPC5747CFK0AMKU6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5747CFK0AMKU6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5747CFK0AMKU6?
SPC5747CFK0AMKU6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5747CFK0AMKU6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5747CFK0AMKU6?
For technical support, including SPC5747CFK0AMKU6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5747CFK0AMKU6 requirements.
6.How does Aetrix verify that SPC5747CFK0AMKU6 is sourced from the original manufacturer or authorized distributors?
All SPC5747CFK0AMKU6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5747CFK0AMKU6 meets industry standards.
7.What is the process for return or replacement of SPC5747CFK0AMKU6?
All SPC5747CFK0AMKU6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5747CFK0AMKU6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5747CFK0AMKU6 part is unused and in its original packaging.
Return procedure for SPC5747CFK0AMKU6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SPC5747CFK0AMKU6 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

