NXP Semiconductors SPC5747CK1CMJ2R

Overview

SPC5747CK1CMJ2R from NXP Semiconductors is an automotive-qualified Power Architecture® microcontroller featuring dual e200z4 cores (160 MHz) and one e200z2 core (80 MHz), 4 MB on-chip flash, 512 KB SRAM, end-to-end ECC, and ASIL-B-certifiable functional safety support. It integrates eight FlexCAN modules with optional CAN FD, four DSPI, six SPI, 18 LINFlexD, three SAI, Ethernet switch capability, and hardware security module (HSMv2) for secure boot and lifecycle management - deployed in vehicle gateway and body control units.

For engineers reviewing the SPC5747CK1CMJ2R datasheet, SPC5747CK1CMJ2R pinout, SPC5747CK1CMJ2R application, or SPC5747CK1CMJ2R equivalent, this page delivers verified technical context, validated pin-level design meaning, confirmed automotive-grade operating parameters, and two rigorously cross-referenced alternative parts for gateway and domain controller designs requiring ISO 26262 compliance, multi-protocol connectivity, and deterministic real-time execution.

Technical Context

The SPC5747CK1CMJ2R implements a triple-core heterogeneous architecture: two high-performance e200z4 CPUs (160 MHz, VLE, single-precision FPU, 8 KB I-cache/4 KB D-cache) plus one e200z2 CPU (80 MHz, VLE) - all with SECDED ECC on all bus transactions across 64-bit data and 29-bit address paths. Its memory subsystem includes 4 MB flash (with 3-port controller and BAF serial programming), 512 KB SRAM across three ports, and dual SMPUs (12-region each) for memory protection.

Peripheral integration centers on automotive networking: eight FlexCAN3 controllers (CAN FD-capable), 18 LINFlexD modules, four DSPI, six SPI, three SAI with fractional clock dividers, dual-channel FlexRay, ENET complex with AVB/IEEE 1588 support, and USB OTG/SPH. Clocking uses FMPLL with FXOSC (8–40 MHz), SXOSC (32 kHz), FIRC (16 MHz), and SIRC (128 kHz), while safety is enforced via HSMv2, FCCU fault collection, and ISO 26262 ASIL-B-certifiable functions.

Key Specifications

Pinout & Package

SPC5747CK1CMJ2R is housed in a 256-pin MAPBGA (package code MJ), with 15 mm × 15 mm body size, 0.8 mm ball pitch, and thermal pad exposed on underside for enhanced heat transfer in automotive under-hood environments.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar automotive microcontroller applications.

Compared with MPC5748GK1MJ2R and SPC5746CK1CMJ2R, the SPC5747CK1CMJ2R delivers optimal balance of flash capacity (4 MB), integrated HSMv2, and full FlexCAN/LIN/Ethernet connectivity for ASIL-B gateway applications - avoiding over-specification while maintaining upgrade path to MPC5748G.

Availability

SPC5747CK1CMJ2R is available at Aetrix Electronics and suitable for vehicle gateway controllers, body control modules, and chassis domain controllers requiring stable component supply, long-term automotive qualification, and ISO 26262-compliant lifecycle support.

Supply support for SPC5747CK1CMJ2R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Power Architecture®, ARM-based MCUs, and automotive functional safety.

The SPC5747C product line targets automotive domain controllers and gateways, delivering ASIL-B-certifiable real-time performance, multi-protocol connectivity (CAN FD, LIN, FlexRay, Ethernet), and hardware-enforced security - designed specifically for next-generation E/E architectures.

FAQ

What is the maximum operating frequency of the SPC5747CK1CMJ2R cores?

The SPC5747CK1CMJ2R features two e200z4 cores operating at up to 160 MHz and one e200z2 core at up to 80 MHz. These frequencies are guaranteed across the full automotive temperature range (–40°C to +125°C ambient) under specified voltage conditions (VDD_LV = 1.2–1.32 V, VDD_HV = 3.15–3.6 V or 4.5–5.5 V), as validated in NXP's characterization reports and Rev. 6 datasheet Section 4.2.

Does the SPC5747CK1CMJ2R support CAN FD, and how many interfaces are available?

Yes, the SPC5747CK1CMJ2R supports CAN FD on all eight integrated FlexCAN3 modules. Each module is configurable for classical CAN or CAN FD operation with bit rates up to 5 Mbps in FD mode, as documented in the MPC5748G family datasheet Section 6.4.2 and Table 1. This capability is retained in the SPC5747C variant per NXP's family comparison matrix.

What safety certifications apply to the SPC5747CK1CMJ2R?

The SPC5747CK1CMJ2R is ISO 26262 ASIL-B-certifiable, with hardware features including end-to-end ECC, dual SMPUs, FCCU fault collection unit, lockstep-capable timers (PIT/SWT), and certified safety libraries. NXP provides FMEDA reports, safety manuals, and diagnostic coverage data aligned to ASIL-B requirements - confirmed in the MPC5748G datasheet Section 2 and safety documentation package.

Is hardware security (HSM) included in the SPC5747CK1CMJ2R?

Yes, the SPC5747CK1CMJ2R integrates HSMv2 (Hardware Security Module version 2), supporting secure boot, AES-128/256 and SHA-256 acceleration, key provisioning, and tamper detection. This is explicitly listed in the MPC5748G family comparison table (Table 1) under "HSM-v2 (security)" for the "G" and "C" variants, and confirmed in the SPC5747C ordering code structure where "K" denotes HSM inclusion.

What package type and pin count does the SPC5747CK1CMJ2R use?

The SPC5747CK1CMJ2R uses a 256-pin MAPBGA package (code MJ), with 15 mm × 15 mm body size and 0.8 mm ball pitch. This is defined in NXP's ordering information (Section 3.2), where "MJ" maps unambiguously to the 256-ball variant - distinct from KU (176 LQFP-EP) and MN (324 BGA) options in the same family.