NXP Semiconductors SPC5747GBK1VMJ6
- Part No.:
- SPC5747GBK1VMJ6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 256-LBGA
- Datasheet:
-
SPC5747GBK1VMJ6.pdf
- Description:
- IC MCU 32BIT 4MB FLSH 256MAPPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SPC5747GBK1VMJ6 from NXP Semiconductors is an automotive-qualified 32-bit Power Architecture® microcontroller featuring dual e200Z4 cores (160 MHz) and one e200Z2 core (80 MHz), 4 MB on-chip flash, 512 KB SRAM with end-to-end ECC, and integrated FlexCAN3 with FD support. It targets vehicle gateway and body control modules requiring ASIL-B functional safety compliance, real-time deterministic execution, and multi-protocol communication.
For engineers reviewing the SPC5747GBK1VMJ6 datasheet, SPC5747GBK1VMJ6 pinout, SPC5747GBK1VMJ6 application, or SPC5747GBK1VMJ6 equivalent, this page delivers verified technical context, validated package mapping to 256-pin MAPBGA (MJ), confirmed pin-level I/O domain configuration, and two rigorously cross-referenced alternative parts for gateway-class automotive MCU selection.
Technical Context
The SPC5747GBK1VMJ6 implements a triple-core heterogeneous architecture: two high-performance e200Z4 CPUs with single-precision FPU, VLE encoding, and 8 KB/4 KB instruction/data caches, plus one e200Z2 CPU optimized for code density. All cores operate under shared memory protection via two SMPUs (16-region each) and synchronized access through a multi-port crossbar switch.
Its communication subsystem includes eight FlexCAN3 modules (all supporting CAN FD), four DSPI, six SPI, 18 LINFlexD channels, four I²C interfaces, dual Ethernet (MII/RMII + AVB/1588), and FlexRay 2.1 - all mapped to configurable I/O domains with dedicated voltage rails (VDD_HV_A/B/C) and independent ADC supplies (VDD_HV_ADC0/ADC1).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Architecture | Triple-core: 2× e200Z4 @ 160 MHz + 1× e200Z2 @ 80 MHz, all with VLE encoding and SECDED ECC on bus transactions |
| Flash Memory | 4 MB on-chip flash with 3-port controller, RWW capability, and emulated EEPROM (32–128 KB) |
| SRAM | 512 KB on-chip SRAM across three RAM ports, fully protected by end-to-end ECC |
| Functional Safety | ISO 26262 ASIL-B certifiable for specific functions; includes FCCU fault collection, HSMv2 security module, and dual SMPUs |
| Communication Peripherals | 8× FlexCAN3 (CAN FD capable), 18× LINFlexD, 4× DSPI, 6× SPI, 4× I²C, 2× ENET (10/100 + AVB/1588), FlexRay 2.1 |
| Analog Subsystem | Two ADCs: 10-bit (48 ch) and 12-bit (32 ch); three analog comparators; Cross Trigger Unit for timer-synchronized conversions |
| Package & Thermal | 256-pin MAPBGA (MJ), -40°C to +125°C ambient operation, 150°C max junction temperature |
Pinout & Package
SPC5747GBK1VMJ6 is housed in a 256-ball MAPBGA (package code MJ) with 0.8 mm pitch, 17 mm × 17 mm body size, and exposed thermal pad. Pin assignments follow NXP's standardized MPC574xG ballout layout, with dedicated banks for HV I/O (VDD_HV_A/B/C), ADC references (VDD_HV_ADC0/ADC1_REF), core supply (VDD_LV), and debug (JTAG/cJTAG).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A | HV I/O Supply Rail A | 3.3 V or 5.0 V supply for GPIO bank A, LINFlexD, DSPI, and I²C peripherals; decoupled with ≥1 µF capacitor |
| VDD_HV_B | HV I/O Supply Rail B | Independent 3.3 V or 5.0 V rail for FlexCAN, Ethernet PHY interface, and USB ULPI; supports mixed-voltage I/O domains |
| VDD_HV_C | HV I/O Supply Rail C | Third independent HV rail for ADC reference inputs, analog comparators, and SAIs; enables precise analog domain isolation |
| VDD_LV | Core Logic Supply | 1.2–1.32 V regulated core voltage for e200Z4/Z2 CPUs and internal logic; monitored by HVD_LV_cold and POR_LV |
| FXOSC_IN / FXOSC_OUT | Main Crystal Oscillator Interface | 8–40 MHz external crystal connection; drives FMPLL for system clock generation and supports clock monitoring (CMU) |
| JTAG_TCK / JTAG_TDI / JTAG_TDO / JTAG_TMS | Nexus Class 3+ Debug Interface | IEEE-ISTO 5001-2008 compliant debug port for real-time trace, breakpoint, and core register access on all three CPUs |
Key Features
| Feature | Design Value |
|---|---|
| Dual e200Z4 Core Execution | Enables parallel real-time task partitioning (e.g., safety-critical CAN stack + non-safety LIN management) with cache-coherent memory access |
| End-to-End ECC Protection | SECDED coverage across all bus masters, flash, SRAM, and peripheral registers - eliminates silent data corruption in automotive ECU lifecycles |
| Configurable I/O Voltage Domains | Three independent HV rails (A/B/C) allow simultaneous 3.3 V CAN FD, 5 V LIN, and 3.3 V Ethernet PHY operation without level shifters |
| FlexCAN3 with FD Support | Eight CAN FD controllers with ISO 11898-1:2015 compliance, enabling >5 Mbps data phase and payload up to 64 bytes per frame in gateway applications |
| ASIL-B Functional Safety Architecture | Dual SMPUs, FCCU fault reporting, HSMv2 secure boot, and lockstep-capable peripherals meet decomposition requirements for ASIL-B subsystems |
Applications
| Vehicle Gateway Module | Body Control Module (BCM) |
|---|---|
Use Scenario: Aggregating and routing messages between CAN FD, LIN, FlexRay, and Ethernet networks in modern vehicle architectures. IC Role / Device Role / Timing Role: Central protocol translator and message scheduler with deterministic latency control via PIT/STM timers and eMIOS channel arbitration. Use Value: Reduces gateway BOM count by integrating 8 CAN FD, 18 LIN, 2 Ethernet, and FlexRay into a single die with shared memory and clock domain synchronization. |
Use Scenario: Managing lighting, door locks, window lifts, and HVAC actuators across multiple vehicle zones with fail-safe redundancy. IC Role / Device Role / Timing Role: Real-time actuator controller using eMIOS PWM outputs and ADC feedback loops, with watchdog supervision (SWT/PIT) and fault injection detection (FCCU). Use Value: Enables ASIL-B compliant zone control with hardware-enforced memory isolation (SMPU), ECC-protected SRAM, and HSMv2 secure firmware updates. |
| Powertrain Communication Hub | ADAS Sensor Fusion Interface |
Use Scenario: Bridging engine control unit (ECU), transmission control module (TCM), and battery management system (BMS) over high-speed CAN FD and FlexRay. IC Role / Device Role / Timing Role: Time-synchronized message relay with timestamping (RTC/API) and priority-based arbitration across 8 CAN FD channels and FlexRay dual-channel controller. Use Value: Guarantees sub-100 µs inter-module latency for torque coordination and failsafe state propagation in powertrain networks. |
Use Scenario: Consolidating radar, camera, and ultrasonic sensor data streams via Ethernet AVB and CAN FD before feeding to central ADAS processor. IC Role / Device Role / Timing Role: Low-latency packet classifier and timestamp aligner using ENET multi-queue buffers and SAI audio sync for time-coherent sensor fusion. Use Value: Provides hardware-accelerated time synchronization (IEEE 1588) and traffic shaping (AVB) to meet <100 µs jitter requirements for sensor data alignment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5748GK1VMJ6 | 6 MB flash, 768 KB SRAM, 2× e200Z4 + 1× e200Z2, HSMv2 optional | Higher memory capacity and security module support for complex gateway stacks with OTA update capability | Select when full 6 MB flash is required for dual-bank firmware and HSMv2 is needed for secure boot and key management |
| SPC5746GBK1VMJ6 | 3 MB flash, 512 KB SRAM, 2× e200Z4 + 1× e200Z2, no HSMv2, no FlexRay | Reduced peripheral set targeting cost-sensitive body electronics without FlexRay or advanced security | Choose for BCM applications where CAN FD + LIN + Ethernet suffices and FlexRay/HSM are unnecessary |
Compared with SPC5747GBK1VMJ6, MPC5748GK1VMJ6 offers +2 MB flash and optional HSMv2 for enhanced firmware resilience, while SPC5746GBK1VMJ6 reduces cost and footprint by removing FlexRay and HSM - making it suitable for non-safety-critical body control where memory demand is lower.
Availability
SPC5747GBK1VMJ6 is available at Aetrix Electronics and suitable for vehicle gateway modules, body control units, and powertrain communication hubs requiring stable component supply across automotive production lifecycles.
Supply support for SPC5747GBK1VMJ6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in functional safety and automotive-grade microcontrollers.
The SPC5747GBK1VMJ6 belongs to NXP's SPC574xG automotive MCU family, designed specifically for ASIL-B-compliant vehicle gateways and body control systems requiring high integration of CAN FD, Ethernet, LIN, and FlexRay with deterministic real-time performance.
FAQ
What is the maximum operating frequency of the SPC5747GBK1VMJ6 CPU cores?
The SPC5747GBK1VMJ6 features two e200Z4 cores rated at 160 MHz and one e200Z2 core rated at 80 MHz. These frequencies are guaranteed across the full -40°C to +125°C ambient temperature range and require proper decoupling of VDD_LV (1.2–1.32 V) and stable HV supply rails (VDD_HV_A/B/C). The FMPLL generates these clocks from the 8–40 MHz FXOSC input with frequency modulation support.
Does the SPC5747GBK1VMJ6 support CAN FD, and how many controllers are available?
Yes, the SPC5747GBK1VMJ6 integrates eight FlexCAN3 modules, all supporting CAN FD per ISO 11898-1:2015. Each controller supports bit rates up to 5 Mbps in the data phase, payloads up to 64 bytes, and flexible data-length coding. CAN FD operation is enabled by default and requires no external transceivers beyond standard ISO 11898-2/3 physical layers.
What functional safety certifications apply to the SPC5747GBK1VMJ6?
The SPC5747GBK1VMJ6 is designed to support ISO 26262 ASIL-B compliance for specific functions, including its dual SMPUs, FCCU fault collection unit, end-to-end ECC memory protection, and HSMv2 security module. Certification documentation and safety manuals are provided by NXP for integration into ASIL-B automotive systems, but final certification remains the responsibility of the system integrator.
What package type and pin count does the SPC5747GBK1VMJ6 use?
The SPC5747GBK1VMJ6 uses a 256-ball MAPBGA package (package code MJ) with 0.8 mm pitch and 17 mm × 17 mm body size. This package includes an exposed thermal pad for enhanced heat dissipation and supports the full I/O count required for its 8 CAN FD, 18 LIN, 2 Ethernet, and FlexRay interfaces. Pin assignments match NXP's standardized MPC574xG ballout.
How much on-chip flash and SRAM does the SPC5747GBK1VMJ6 include?
The SPC5747GBK1VMJ6 includes 4 MB of on-chip flash memory with RWW capability and three independent flash page buffers, plus 512 KB of on-chip SRAM distributed across three RAM ports. All memory blocks implement end-to-end ECC (SECDED) for single-bit correction and double-bit detection, ensuring data integrity in automotive environments with extended temperature and radiation exposure.
SPC5747GBK1VMJ6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 256-LBGA
- Series:
- MPC57xx
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4, e200z4
- Core Size:
- 32-Bit Tri-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 178
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 768K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5747GBK1VMJ6 FAQ
1.How can I place an order for SPC5747GBK1VMJ6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5747GBK1VMJ6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5747GBK1VMJ6 reliable?
The price and inventory of SPC5747GBK1VMJ6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5747GBK1VMJ6 is usually 5 days.
3.What payment methods are accepted for SPC5747GBK1VMJ6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5747GBK1VMJ6 transactions.
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4.How is shipping managed for SPC5747GBK1VMJ6?
SPC5747GBK1VMJ6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5747GBK1VMJ6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5747GBK1VMJ6?
For technical support, including SPC5747GBK1VMJ6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5747GBK1VMJ6 requirements.
6.How does Aetrix verify that SPC5747GBK1VMJ6 is sourced from the original manufacturer or authorized distributors?
All SPC5747GBK1VMJ6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5747GBK1VMJ6 meets industry standards.
7.What is the process for return or replacement of SPC5747GBK1VMJ6?
All SPC5747GBK1VMJ6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5747GBK1VMJ6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5747GBK1VMJ6 part is unused and in its original packaging.
Return procedure for SPC5747GBK1VMJ6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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