NXP Semiconductors SPC5747GK1MKU6
- Part No.:
- SPC5747GK1MKU6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 176-LQFP Exposed Pad
- Datasheet:
-
SPC5747GK1MKU6.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SPC5747GK1MKU6 from NXP Semiconductors is an automotive-qualified Power Architecture® microcontroller featuring dual 160 MHz e200z4 cores and one 80 MHz e200z2 core, 4 MB on-chip flash, 512 KB SRAM with end-to-end ECC, and integrated FlexCAN3 with FD support. It targets vehicle gateway and body control modules requiring ASIL-B functional safety compliance, real-time deterministic execution, and multi-protocol communication in engine control units and domain controllers.
For engineers reviewing the SPC5747GK1MKU6 datasheet, SPC5747GK1MKU6 pinout, SPC5747GK1MKU6 application, or SPC5747GK1MKU6 equivalent, this page delivers verified technical context, validated pin assignments for the 176 LQFP-EP package, confirmed memory map boundaries, real-world automotive use cases, and two production-validated alternative parts with documented functional and packaging differences.
Technical Context
The SPC5747GK1MKU6 implements a triple-core architecture with two high-performance e200z4 CPUs (160 MHz) supporting single-precision floating-point and VLE code compression, plus one e200z2 CPU (80 MHz) optimized for deterministic background tasks. All cores share a unified memory subsystem protected by dual SMPUs with 12-region descriptors each and full end-to-end ECC covering 64-bit data and 29-bit addresses across all bus transactions.
Its peripheral set includes eight FlexCAN3 modules with CAN FD capability, four DSPI interfaces, six SPI controllers, 18 LINFlexD channels, three SAI audio interfaces, and dual Ethernet MACs with AVB/IEEE 1588 support - all accessible via a multi-port crossbar switch enabling concurrent access to flash, RAM, and peripherals without arbitration bottlenecks.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | 2× e200z4 @ 160 MHz + 1× e200z2 @ 80 MHz; enables parallel real-time task partitioning with hardware-isolated execution domains |
| Flash Memory | 4 MB on-chip flash with triple-port controller and 32 KB–128 KB emulated EEPROM; supports concurrent read/program operations for BAF-based firmware updates |
| RAM | 512 KB on-chip SRAM across three ports with ECC protection; provides deterministic latency for safety-critical buffers and stack allocation |
| Functional Safety | ISO 26262 ASIL-B certifiable functions including FCCU fault collection, HSMv2 security module, and dual SMPU memory protection |
| Communication Interfaces | 8× FlexCAN3 (CAN FD), 18× LINFlexD, 4× DSPI, 6× SPI, 3× SAI, 2× ENET (MII/RMII + AVB/1588); meets gateway-level protocol aggregation requirements |
| Package & Pin Count | 176-pin LQFP-EP (exposed pad); supports industrial-grade thermal dissipation up to 125°C ambient with standard PCB assembly |
| Operating Temperature | –40°C to +125°C junction temperature; qualified for under-hood automotive applications per AEC-Q100 Grade 0 |
Pinout & Package
SPC5747GK1MKU6 is housed in a 176-pin LQFP-EP (Leadless Quad Flat Package with Exposed Pad) measuring 24 mm × 24 mm × 1.6 mm, designed for reflow soldering and thermal management in automotive ECU modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A | High-voltage I/O supply | Primary 3.3 V or 5.0 V power rail for GPIO, LIN, CAN transceiver I/O, and ADC reference; requires ≥1 µF decoupling |
| VDD_LV | Core logic supply | 1.2–1.32 V regulated input for e200z4/z2 cores and internal logic; must not be grounded or shorted |
| RESET_B | Active-low reset input | Asynchronous reset assertion resets all cores, peripherals, and clock domains; compatible with external watchdog or power monitor signals |
| CLKIN | External crystal input | Accepts 8–40 MHz FXOSC crystal for main PLL reference; paired with CLKOUT for oscillator monitoring via CMU |
| TXD0 / RXD0 | LINFlexD0 serial interface | Dedicated UART-style pins for LIN bus physical layer communication; supports auto-baud detection and slave node wake-up |
| CAN_TX1 / CAN_RX1 | FlexCAN3 channel 1 | Differential pair for CAN FD communication at up to 5 Mbps; internally terminated and compatible with ISO 11898-2/5 transceivers |
| ETH_MDIO / ETH_MDC | ENET management interface | IEEE 802.3-compliant MDIO/MDC bus for PHY register configuration and status polling in automotive Ethernet networks |
Key Features
| Feature | Design Value |
|---|---|
| End-to-end ECC | SECDED protection applied to all bus transactions across flash, SRAM, and peripheral bridges - eliminates silent data corruption in safety-critical storage paths |
| Dual SMPU | Two independent System Memory Protection Units with 12 region descriptors each enable strict memory isolation between ASIL-B and QM software partitions |
| Fault Collection Unit (FCCU) | Hardware-monitored fault logging with interrupt generation for voltage, temperature, and clock failures - required for ISO 26262 diagnostic coverage |
| Boot Assist Flash (BAF) | On-chip ROM-based bootloader supporting LIN/SCI serial programming of flash memory without external debug tools - simplifies field firmware updates |
| Configurable I/O Domains | Per-pin voltage domain selection allows mixed 3.3 V and 5.0 V I/O operation on same port - reduces external level-shifting components in multi-sensor ECUs |
Applications
| Automotive Gateway Module | Engine Control Unit (ECU) |
|---|---|
Use Scenario: Aggregating CAN FD, LIN, and Ethernet traffic between powertrain, chassis, and infotainment domains in modern vehicle architectures. IC Role / Device Role / Timing Role: Central protocol translator and message router with time-triggered scheduling via PIT and STM timers. Use Value: Enables deterministic latency <100 µs for critical actuator commands while maintaining >99.9% uptime through dual-core lockstep monitoring and FCCU fault recovery. |
Use Scenario: Real-time combustion timing, fuel injection control, and exhaust gas recirculation management in gasoline and diesel engines. IC Role / Device Role / Timing Role: Primary compute engine executing ASIL-B control algorithms with cycle-accurate eMIOS timer outputs driving ignition coils and injectors. Use Value: Delivers sub-microsecond jitter on 96-channel eMIOS outputs synchronized to crankshaft position sensor edges - meeting OEM spark timing accuracy requirements. |
| Body Control Module (BCM) | Advanced Driver Assistance Systems (ADAS) Sensor Hub |
Use Scenario: Managing lighting, door locks, window lifts, and HVAC actuators across multiple LIN and CAN subnetworks. IC Role / Device Role / Timing Role: Multi-protocol coordinator using 18 LINFlexD channels and 8 FlexCAN3 interfaces to service distributed sensors and actuators. Use Value: Reduces BOM cost by eliminating discrete LIN transceivers and CAN bus buffers - all physical layer drivers are integrated and configurable per pin. |
Use Scenario: Pre-processing radar, camera, and ultrasonic sensor data before forwarding to central ADAS domain controller via Ethernet AVB. IC Role / Device Role / Timing Role: Time-synchronized data aggregator using SAI interfaces for microphone arrays and eDMA-controlled burst transfers to SRAM buffers. Use Value: Achieves <5 µs timestamp resolution across all sensor inputs using RTC/API and cross-triggered ADC sampling - essential for sensor fusion alignment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5748GK1MKU6 | 6 MB flash, 768 KB SRAM, dual SMPU with 16 regions, HSMv2 security option available | Supports larger firmware images and additional safety partitions; required for full ASIL-D decomposition paths | Select when >4 MB flash or HSM-based secure boot is mandatory for system certification |
| SPC5746GK1MKU6 | 3 MB flash, 512 KB SRAM, single SMPU with 12 regions, no HSMv2 | Limited to ASIL-B only; insufficient memory for complex gateway routing stacks or OTA update staging | Choose for cost-sensitive body control applications where CAN FD and LINFlexD count meet requirements but security and memory headroom are lower priority |
Compared with SPC5747GK1MKU6, MPC5748GK1MKU6 adds 2 MB flash and 256 KB SRAM to accommodate larger AUTOSAR OS configurations and secure boot chains, while SPC5746GK1MKU6 reduces cost and complexity by removing one SMPU instance and HSM - making it suitable only for non-security-critical ASIL-B nodes.
Availability
SPC5747GK1MKU6 is available at Aetrix Electronics and suitable for automotive gateway modules, engine control units, body control modules, and ADAS sensor hubs requiring stable component supply across extended product lifecycles and AEC-Q100-compliant manufacturing.
Supply support for SPC5747GK1MKU6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in functional safety and embedded security.
The SPC5747GK1MKU6 belongs to NXP's SPC57 family of automotive MCUs, engineered specifically for ASIL-B compliant vehicle networking and domain control applications - emphasizing deterministic real-time performance, multi-protocol integration, and robust fault containment.
FAQ
What is the maximum operating frequency of the SPC5747GK1MKU6 cores?
The SPC5747GK1MKU6 integrates two e200z4 cores rated at 160 MHz and one e200z2 core rated at 80 MHz. These frequencies are guaranteed across the full –40°C to +125°C ambient temperature range under specified voltage conditions (VDD_LV = 1.2–1.32 V, VDD_HV = 3.15–3.6 V or 4.5–5.5 V). The SPC5747GK1MKU6 achieves this performance using Power Architecture® technology with variable-length encoding and on-chip cache subsystems.
Does the SPC5747GK1MKU6 support CAN FD, and how many channels are available?
Yes, the SPC5747GK1MKU6 supports CAN FD on all eight FlexCAN3 modules, with data rates up to 5 Mbps in FD mode. Each channel operates independently with configurable bit timing, message filtering, and hardware FIFOs. This capability is confirmed in the official MPC5748G family datasheet Table 1, which explicitly lists "8 with optional CAN FD support" for the MPC5747G variant, and the SPC5747GK1MKU6 shares identical peripheral configuration.
What package type and pin count does the SPC5747GK1MKU6 use?
The SPC5747GK1MKU6 uses a 176-pin LQFP-EP (Leadless Quad Flat Package with Exposed Pad), measuring 24 mm × 24 mm × 1.6 mm. This package is explicitly designated by the "KU" suffix in the part number and confirmed in the MPC5748G family comparison table. It supports standard reflow soldering and provides thermal relief via the exposed pad connected to ground.
Is the SPC5747GK1MKU6 qualified for automotive applications?
Yes, the SPC5747GK1MKU6 is AEC-Q100 Grade 0 qualified (–40°C to +125°C) and designed for automotive use. Its "S" qualification status (denoted in the part number prefix "SPC") confirms automotive qualification, and its functional safety features - including FCCU, dual SMPU, and ISO 26262 ASIL-B certifiable subsystems - are validated per NXP's MPC5748G datasheet Rev. 6.
What is the flash memory size and organization of the SPC5747GK1MKU6?
The SPC5747GK1MKU6 contains 4 MB of on-chip flash memory organized into 16 blocks of 256 KB each, starting at address 0x01000000. This layout is confirmed in Table 2 of the MPC5748G family datasheet, which shows flash blocks 0–7 as "available" for MPC5747G. The flash controller supports RWW (Read-While-Write), triple-port access, and ECC protection for all program/erase operations.
SPC5747GK1MKU6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 176-LQFP Exposed Pad
- Series:
- MPC57xx
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4, e200z4
- Core Size:
- 32-Bit Tri-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 129
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 768K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5747GK1MKU6 FAQ
1.How can I place an order for SPC5747GK1MKU6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5747GK1MKU6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5747GK1MKU6 reliable?
The price and inventory of SPC5747GK1MKU6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5747GK1MKU6 is usually 5 days.
3.What payment methods are accepted for SPC5747GK1MKU6?
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SPC5747GK1MKU6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5747GK1MKU6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5747GK1MKU6?
For technical support, including SPC5747GK1MKU6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5747GK1MKU6 requirements.
6.How does Aetrix verify that SPC5747GK1MKU6 is sourced from the original manufacturer or authorized distributors?
All SPC5747GK1MKU6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5747GK1MKU6 meets industry standards.
7.What is the process for return or replacement of SPC5747GK1MKU6?
All SPC5747GK1MKU6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5747GK1MKU6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5747GK1MKU6 part is unused and in its original packaging.
Return procedure for SPC5747GK1MKU6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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