NXP Semiconductors SPC5748CK1MKU6
- Part No.:
- SPC5748CK1MKU6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 176-LQFP Exposed Pad
- Datasheet:
-
SPC5748CK1MKU6.pdf
- Description:
- IC MCU 32BIT 6MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SPC5748CK1MKU6 from NXP Semiconductors is an automotive-qualified Power Architecture® microcontroller featuring dual 160 MHz e200Z4 cores and one 80 MHz e200Z2 core, 6 MB on-chip flash, 768 KB SRAM with end-to-end ECC, and integrated FlexCAN FD, Ethernet AVB, and HSMv2 security. It targets vehicle gateway and domain controller applications requiring ASIL-B functional safety compliance.
For engineers reviewing the SPC5748CK1MKU6 datasheet, SPC5748CK1MKU6 pinout, SPC5748CK1MKU6 application, or SPC5748CK1MKU6 equivalent, this page delivers verified technical context, validated pin mapping for the 176 LQFP-EP package, real-world use cases in automotive networking, and two confirmed alternative parts with documented functional and packaging differences.
Technical Context
The SPC5748CK1MKU6 implements a triple-core heterogeneous architecture: two high-performance e200Z4 CPUs (160 MHz, VLE, single-precision FPU, 8 KB I-cache/4 KB D-cache) plus one e200Z2 CPU (80 MHz, VLE), all sharing a 64-bit AHB bus with end-to-end SECDED ECC across flash, RAM, and interconnects. Its memory subsystem includes 6 MB flash with three port buffers and 768 KB SRAM distributed across three ports with SMPU protection.
Peripheral integration centers on automotive networking: eight FlexCAN modules (all supporting CAN FD), dual 10/100 Ethernet controllers with AVB, IEEE 1588, and L2 switching, dual-channel FlexRay 2.1, 18 LINFlexD channels, and hardware security via HSMv2 with PASS/TDM lifecycle management - all coordinated under ISO 26262 ASIL-B certification scope.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Architecture | Triple-core: dual 160 MHz e200Z4 + one 80 MHz e200Z2, all with VLE and SECDED ECC |
| Flash Memory | 6 MB on-chip flash with triple-port controller, RWW support, and emulated EEPROM up to 192 KB |
| RAM | 768 KB on-chip SRAM across three independent ports, all protected by ECC |
| Functional Safety | ISO 26262 ASIL-B certified; includes FCCU fault collection, MBIST/LBIST, and dual SMPUs (16-region each) |
| Automotive Interfaces | 8 × FlexCAN FD, 2 × 10/100 Ethernet with AVB/1588/MII/RMII, dual FlexRay 2.1, 18 × LINFlexD |
| Security | HSMv2 with cryptographic acceleration, PASS/TDM for device censorship and life-cycle management |
| Package & Temp | 176-pin LQFP-EP, -40°C to +125°C ambient operating range (automotive qualification) |
Pinout & Package
SPC5748CK1MKU6 is housed in a 176-pin Low-Profile Quad Flat Package with Exposed Pad (LQFP-EP), optimized for thermal dissipation in automotive control units. Pin assignments follow NXP's standardized MPC5748G signal multiplexing scheme, with dedicated power domains (VDD_HV_A/B/C, VDD_LV), I/O banks supporting configurable voltage levels (3.3 V or 5 V), and dedicated debug (JTAG/cJTAG) and boot (LIN/SCI) interfaces.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / VDD_HV_B / VDD_HV_C | High-voltage I/O supply inputs | Independent 3.3 V or 5 V supplies for I/O banks; enable mixed-voltage interface design |
| VDD_LV | Core logic supply input | 1.2–1.32 V supply for e200Z4/Z2 cores; requires external decoupling per regulator spec |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Supports 8–40 MHz external crystal for primary clock source with CMU monitoring |
| JTAG_TCK / TMS / TDI / TDO / TRST | Nexus Class 3+ debug interface | IEEE-ISTO 5001-2008 compliant; enables full-core visibility, trace, and secure debug access |
| LIN0_TX / LIN0_RX | Primary LIN communication channel | Dedicated LINFlexD module supporting LIN 2.x protocol and wake-up from low-power modes |
| CAN0_TX / CAN0_RX | First FlexCAN FD transceiver interface | Supports CAN FD data rates up to 5 Mbit/s; integrated bus-off recovery and error counters |
| ETH0_MDC / MDIO / TXD[3:0] / RXD[3:0] | First Ethernet PHY interface | MII/RMII-capable; enables AVB streaming and IEEE 1588 timestamping at physical layer |
Key Features
| Feature | Design Value |
|---|---|
| End-to-end ECC protection | SECDED applied to all bus transactions across flash, SRAM, and interconnects - eliminates silent data corruption in safety-critical paths |
| Dual SMPU with 16-region granularity | Enables fine-grained memory access control per core/peripheral; supports ASIL-B partitioning of software components |
| HSMv2 with PASS/TDM | Hardware-accelerated crypto engine with secure boot, key provisioning, and tamper-resistant lifecycle management |
| Fault Collection and Control Unit (FCCU) | Centralized fault logging and response coordination across cores, peripherals, and memory - required for ASIL-B diagnostics |
| Configurable I/O domains | Per-bank voltage selection (3.3 V/5 V) and pad keeper support allow mixed-signal interfacing without level shifters |
Applications
| Body Control Module (BCM) | Vehicle Gateway |
|---|---|
Use Scenario: Centralized management of lighting, door locks, window lifts, and HVAC actuators in modern vehicles. IC Role / Device Role / Timing Role: Primary application MCU executing real-time control tasks, coordinating LIN/FlexCAN traffic, and managing power states via WKPU. Use Value: 768 KB ECC-protected SRAM enables concurrent execution of multiple AUTOSAR-compliant ECUs; 18 LINFlexD channels eliminate need for external LIN transceivers. |
Use Scenario: Aggregation and routing of CAN FD, Ethernet AVB, and FlexRay messages between ADAS, infotainment, and chassis domains. IC Role / Device Role / Timing Role: High-throughput network bridge with deterministic latency, leveraging dual Ethernet controllers and 8 FlexCAN FD modules. Use Value: Dual 10/100 Ethernet with AVB and IEEE 1588 allows time-synchronized sensor fusion; HSMv2 secures OTA update authentication. |
| Powertrain Communication Hub | Electric Vehicle Battery Management Interface |
Use Scenario: Interfacing engine control unit (ECU), transmission controller, and emissions systems via high-speed CAN FD and LIN. IC Role / Device Role / Timing Role: Deterministic message router with hardware timestamping and priority-based arbitration using FlexCAN FD and eMIOS timers. Use Value: 96-channel eMIOS + 16 PITs enable precise synchronization of spark timing, fuel injection, and OBD-II diagnostics. |
Use Scenario: Monitoring cell voltages, temperatures, and isolation status in high-voltage battery packs using analog front-end and safety-critical firmware. IC Role / Device Role / Timing Role: ASIL-B-certified monitor MCU performing ADC sampling, CRC validation, and fault reporting over CAN FD. Use Value: Dual 10-/12-bit ADCs (64-channel total) with cross-triggering to eMIOS/PIT ensure synchronized sampling across 96 BMS channels. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5746G | 4 MB flash, 512 KB SRAM, no HSMv2, single Ethernet, 6 FlexCAN FD | Lacks dual Ethernet, AVB, and hardware security - suitable for cost-sensitive body control but not gateway or BMS | Select when ASIL-B security and multi-domain networking are not required; lower BOM cost and reduced thermal load |
| S32K344 | ARM Cortex-M7, 4 MB flash, 1.5 MB SRAM, no FlexRay, single Ethernet, HSE security | ARM-based toolchain and AUTOSAR stack; lacks FlexRay and dual Ethernet but offers higher SRAM density | Prefer for new ARM-based designs requiring long-term roadmap continuity; not drop-in compatible due to architecture and pinout mismatch |
Compared with MPC5746G and S32K344, the SPC5748CK1MKU6 uniquely combines Power Architecture performance, FlexRay 2.1, dual Ethernet AVB, and HSMv2 in a single 176-pin LQFP package - making it the only qualified option for legacy Power Architecture gateway upgrades requiring full feature parity.
Availability
SPC5748CK1MKU6 is available at Aetrix Electronics and suitable for automotive gateway systems, electric vehicle battery management interfaces, body control modules, and powertrain communication hubs requiring stable component supply across extended product lifecycles.
Supply support for SPC5748CK1MKU6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in functional safety and automotive-grade microcontrollers.
The SPC5748CK1MKU6 belongs to NXP's SPC57 family of automotive MCUs, designed specifically for vehicle networking and domain control applications demanding ASIL-B compliance, high-speed communication, and hardware-enforced security.
FAQ
What is the core configuration of the SPC5748CK1MKU6?
The SPC5748CK1MKU6 integrates three Power Architecture® cores: two e200Z4 CPUs running at up to 160 MHz each, and one e200Z2 CPU at up to 80 MHz. All cores support Variable Length Encoding (VLE) and share end-to-end ECC-protected memory and bus infrastructure. This configuration is explicitly defined in the MPC5748G datasheet Rev. 6, Section 2 (Family Comparison) and Figure 1 (Block Diagram), and applies directly to the SPC5748CK1MKU6 variant.
Does the SPC5748CK1MKU6 support CAN FD?
Yes, the SPC5748CK1MKU6 supports CAN FD on all eight FlexCAN modules, as confirmed in the MPC5748G datasheet Rev. 6, Table 1 (Family Comparison) and Section 6.4.1 (Communication Interfaces). Each FlexCAN module operates at data rates up to 5 Mbit/s in FD mode and includes hardware timestamping, bus-off recovery, and error counters - essential for high-bandwidth vehicle networking applications.
What package type and pin count does the SPC5748CK1MKU6 use?
The SPC5748CK1MKU6 uses a 176-pin Low-Profile Quad Flat Package with Exposed Pad (LQFP-EP), as indicated by the "KU" suffix in its part number per NXP's ordering guide (Section 3.2). This package is thermally optimized for automotive under-hood environments and supports all I/O features specified for the MPC5748G family, including 246 GPIOs in larger BGA variants - though pin count is fixed at 176 for this LQFP variant.
Is the SPC5748CK1MKU6 qualified for automotive applications?
Yes, the SPC5748CK1MKU6 is automotive-qualified with AEC-Q100 Grade 1 rating (-40°C to +125°C ambient), functional safety compliance to ISO 26262 ASIL-B, and qualification status "S" (Automotive qualified) per NXP's ordering nomenclature. Its design includes hardware fault detection (FCCU), memory built-in self-test (MBIST/LBIST), and dual SMPUs - all validated for automotive ECU deployment.
What security features does the SPC5748CK1MKU6 include?
The SPC5748CK1MKU6 includes HSMv2 (Hardware Security Module version 2) with cryptographic acceleration, Password and Device Security (PASS/TDM) for secure boot and lifecycle management, and a Fault Collection and Control Unit (FCCU) for centralized fault handling. These features are documented in the MPC5748G datasheet Rev. 6, Sections 1 (Features) and 6.5 (Security), and are enabled in the SPC5748CK1MKU6 variant per its "S" qualification and "K" security option code.
SPC5748CK1MKU6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 176-LQFP Exposed Pad
- Series:
- MPC57xx
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 129
- Program Memory Size:
- 6MB (6M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 768K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5748CK1MKU6 FAQ
1.How can I place an order for SPC5748CK1MKU6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5748CK1MKU6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5748CK1MKU6 reliable?
The price and inventory of SPC5748CK1MKU6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5748CK1MKU6 is usually 5 days.
3.What payment methods are accepted for SPC5748CK1MKU6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5748CK1MKU6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5748CK1MKU6?
SPC5748CK1MKU6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5748CK1MKU6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5748CK1MKU6?
For technical support, including SPC5748CK1MKU6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5748CK1MKU6 requirements.
6.How does Aetrix verify that SPC5748CK1MKU6 is sourced from the original manufacturer or authorized distributors?
All SPC5748CK1MKU6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5748CK1MKU6 meets industry standards.
7.What is the process for return or replacement of SPC5748CK1MKU6?
All SPC5748CK1MKU6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5748CK1MKU6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5748CK1MKU6 part is unused and in its original packaging.
Return procedure for SPC5748CK1MKU6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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