NXP Semiconductors SPC5748CK1MMJ6R
- Part No.:
- SPC5748CK1MMJ6R
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 256-LBGA
- Datasheet:
-
SPC5748CK1MMJ6R.pdf
- Description:
- IC MCU 32BIT 6MB FLSH 256MAPPBGA
- Quantity:
- Payment:

- Shipping:

Inventory:3,303
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SPC5748CK1MMJ6R from NXP Semiconductors is an automotive-qualified Power Architecture® microcontroller featuring dual 160 MHz e200Z4 cores and one 80 MHz e200Z2 core, 6 MB on-chip flash, 768 KB SRAM with end-to-end ECC, eight FlexCAN3 modules with CAN FD support, and ISO 26262 ASIL-B-certifiable functional safety architecture - deployed in vehicle gateway and domain controller applications.
For engineers reviewing the SPC5748CK1MMJ6R datasheet, SPC5748CK1MMJ6R pinout, SPC5748CK1MMJ6R application, or SPC5748CK1MMJ6R equivalent, this page delivers verified technical context, validated pin assignments for the 256 MAPBGA package, real-world use cases in automotive networking, and two confirmed alternative parts with documented functional and packaging differences.
Technical Context
The SPC5748CK1MMJ6R implements a heterogeneous multi-core architecture: two high-performance e200Z4 cores (160 MHz, VLE-enabled, single-precision FPU, 8 KB I-cache/4 KB D-cache) plus one e200Z2 core (80 MHz, VLE-only) for dedicated safety or communication management. All cores share a triple-ported 64-bit wide memory subsystem backed by SECDED ECC across flash, SRAM, and bus transactions.
Its peripheral set is optimized for automotive gateway consolidation: eight FlexCAN3 controllers (all supporting CAN FD), four DSPI, six SPI, 18 LINFlexD modules, dual 10/100 Ethernet with AVB and IEEE 1588 support, and a dual-channel FlexRay 2.1 controller - all accessible via multiple crossbar switches enabling concurrent access without arbitration bottlenecks.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Configuration | 2× e200Z4 @ 160 MHz + 1× e200Z2 @ 80 MHz - enables parallel real-time control and safety monitoring with deterministic latency |
| Memory | 6 MB on-chip flash + 768 KB SRAM with end-to-end SECDED ECC - ensures data integrity across boot, runtime, and safety-critical code execution |
| Functional Safety | ISO 26262 ASIL-B certified architecture with HSMv2, FCCU, and SMPUs - supports safety-managed gateway firmware deployment |
| Communication | 8× FlexCAN3 (CAN FD), 2× ENET (10/100 + AVB + 1588), 18× LINFlexD, 4× DSPI, 6× SPI - consolidates body, powertrain, and infotainment network interfaces |
| Package | 256-pin MAPBGA (MJ), 15 mm × 15 mm, 0.8 mm pitch - compatible with automotive PCB assembly standards and thermal requirements up to 125°C ambient |
| Operating Range | –40°C to +125°C ambient temperature, 1.2 V core / 3.3 V or 5 V I/O supply - qualified for under-hood and chassis-mounted ECU environments |
Pinout & Package
SPC5748CK1MMJ6R is housed in a 256-ball MAPBGA (package code MJ), 15 mm × 15 mm, 0.8 mm ball pitch, with exposed thermal pad. Pin assignments follow the MPC5748G family layout per NXP Document Number MPC5748G Rev. 6, Section 9.1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / VDD_HV_B / VDD_HV_C | High-voltage I/O supply domains | Independent 3.3 V or 5 V supplies for configurable I/O banks - enables mixed-voltage interface routing (e.g., 5 V LIN, 3.3 V CAN) |
| VDD_LV | Digital core supply | 1.2–1.32 V regulated input for e200Z4/Z2 cores - requires external decoupling per Table 8 (Clp/ulp_reg = 0.8–1.4 µF) |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | 8–40 MHz external crystal connection - provides primary clock source for FMPLL with ±50 ppm stability requirement |
| CAN0_TX / CAN0_RX | FlexCAN3 channel 0 differential pair | Direct connection to CAN transceiver; supports bit rates up to 5 Mbps with CAN FD - used for high-speed powertrain communication |
| ENET0_MDC / ENET0_MDIO | IEEE 802.3 MII management interface | Serial control bus for PHY configuration - required for AVB stream registration and IEEE 1588 timestamp synchronization |
Key Features
| Feature | Design Value |
|---|---|
| Dual e200Z4 Core Architecture | Enables lockstep or split-mode operation for ASIL-B safety partitioning - each core independently manages separate CAN/FlexRay domains |
| Triple-Ported Flash Controller | Supports concurrent read/program/erase operations - eliminates flash access contention during over-the-air (OTA) update and real-time control execution |
| End-to-End ECC Protection | Covers all bus masters, memory arrays, and interconnect paths - detects and corrects single-bit errors in flash/SRAM/registers without software intervention |
| Hardware Security Module v2 (HSMv2) | Provides secure boot, cryptographic acceleration (AES-128/256, SHA-256), and key lifecycle management - meets UNECE R155/R156 compliance requirements |
| Configurable I/O Domains | Permits independent voltage assignment to LINFlexD, FlexCAN, Ethernet, and USB pins - simplifies integration of legacy 5 V sensors and modern 3.3 V peripherals |
Applications
| Vehicle Gateway | ADAS Domain Controller |
|---|---|
Use Scenario: Aggregating CAN FD, LIN, FlexRay, and Ethernet traffic between powertrain, chassis, and infotainment ECUs in a centralized vehicle architecture. IC Role / Device Role / Timing Role: Primary gateway MCU managing protocol translation, message filtering, and firewall enforcement with sub-100 µs latency guarantees. Use Value: Reduces wiring harness complexity and ECU count by consolidating 8 CAN FD channels, 18 LINFlexD modules, and dual Ethernet with AVB into a single chip. | Use Scenario: Coordinating sensor fusion data from radar, camera, and ultrasonic modules while executing real-time path planning algorithms. IC Role / Device Role / Timing Role: High-integrity compute node running ASIL-B safety monitors alongside non-safety perception stacks using dual e200Z4 cores. Use Value: Enables deterministic execution of time-critical ADAS functions (e.g., emergency braking) with ECC-protected memory and hardware fault collection (FCCU). |
| Electric Powertrain Control | Secure OTA Update Hub |
Use Scenario: Managing battery management system (BMS) communication, motor inverter control, and charging interface protocols in BEV platforms. IC Role / Device Role / Timing Role: Real-time controller interfacing with isolated gate drivers and analog front-ends via eMIOS and ADCs while enforcing functional safety constraints. Use Value: Integrates 96-channel eMIOS for PWM generation, dual ADCs (10-bit + 12-bit), and 8 CAN FD ports - eliminating need for external timing peripherals. | Use Scenario: Authenticating, decrypting, and validating firmware updates received over cellular or Wi-Fi before flashing to internal memory. IC Role / Device Role / Timing Role: Secure boot root-of-trust executing signed update images using HSMv2 and protected flash regions. Use Value: Prevents unauthorized firmware modification via hardware-enforced cryptographic verification and write-protection of critical BAF and security registers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5748GK1MMJ6R | No HSM security module; identical core, memory, and peripheral configuration - lacks HSMv2, PASS/TDM, and secure boot acceleration | Suitable for non-security-critical gateway functions where cryptographic offload is handled externally | Select when cost sensitivity outweighs embedded security requirements and external crypto co-processor is acceptable |
| SPC574SACK1MMJ6R | Reduced peripheral set: 4 FlexCAN (no CAN FD), no Ethernet, no FlexRay, 4 MB flash, 512 KB SRAM - same e200Z4/Z2 cores and ASIL-B foundation | Targeted at cost-optimized body control modules requiring fewer high-speed interfaces | Select for entry-level automotive control where CAN FD, Ethernet, and FlexRay are unnecessary |
Compared with SPC5748CK1MMJ6R, MPC5748GK1MMJ6R removes hardware security but retains full gateway capability, while SPC574SACK1MMJ6R reduces interface count and memory to lower BOM cost - both require PCB redesign due to different peripheral pin mappings and security register layouts.
Availability
SPC5748CK1MMJ6R is available at Aetrix Electronics and suitable for automotive gateway systems, ADAS domain controllers, electric powertrain control units, and secure OTA update hubs requiring stable component supply across extended product lifecycles.
Supply support for SPC5748CK1MMJ6R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The SPC5748CK1MMJ6R belongs to NXP's SPC574x automotive MCU family, designed specifically for ISO 26262-compliant vehicle gateway and domain controller applications requiring high integration, functional safety, and embedded security.
FAQ
What is the core architecture of the SPC5748CK1MMJ6R?
The SPC5748CK1MMJ6R integrates two 160 MHz e200Z4 cores and one 80 MHz e200Z2 core, all based on Power Architecture® with Variable Length Encoding (VLE). Each e200Z4 core includes single-precision floating-point unit, 8 KB instruction cache, and 4 KB data cache. The SPC5748CK1MMJ6R uses this configuration to enable parallel real-time processing and safety partitioning in automotive applications.
Does the SPC5748CK1MMJ6R support CAN FD?
Yes, the SPC5748CK1MMJ6R includes eight FlexCAN3 modules, all of which support CAN FD with data rates up to 5 Mbps. This capability is explicitly confirmed in the MPC5748G datasheet Rev. 6, Section 1 (Block Diagram) and Table 1 (Family Comparison), where "8 with optional CAN FD support" is listed for MPC5748G - and SPC5748CK1MMJ6R is an automotive-qualified variant with HSM enabled.
What package type does the SPC5748CK1MMJ6R use?
The SPC5748CK1MMJ6R uses a 256-ball MAPBGA package (code MJ), measuring 15 mm × 15 mm with 0.8 mm ball pitch and an exposed thermal pad. This matches the MPC5748G family specification in Section 8 (Dimensions) and Table 1 (Family Comparison), confirming mechanical compatibility and thermal performance up to 125°C ambient.
Is the SPC5748CK1MMJ6R ISO 26262 ASIL-B certified?
Yes, the SPC5748CK1MMJ6R implements an ISO 26262 ASIL-B-certifiable architecture, including dual-core lockstep support, Hardware Security Module v2 (HSMv2), Fault Collection and Control Unit (FCCU), System Memory Protection Units (SMPUs), and end-to-end ECC. These features are documented in the MPC5748G datasheet Rev. 6, Section 2 (Family Comparison) and Section 1 (Block Diagram).
What is the flash and RAM capacity of the SPC5748CK1MMJ6R?
The SPC5748CK1MMJ6R contains 6 MB of on-chip flash memory and 768 KB of on-chip SRAM, both protected by end-to-end SECDED ECC. This configuration is confirmed in the MPC5748G datasheet Rev. 6, Table 1 (Family Comparison), where MPC5748G is specified with "6 MB" flash and "768 KB" RAM - and SPC5748CK1MMJ6R is the automotive-qualified, HSM-enabled variant of that part.
SPC5748CK1MMJ6R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 256-LBGA
- Series:
- MPC57xx
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 178
- Program Memory Size:
- 6MB (6M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 768K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5748CK1MMJ6R FAQ
1.How can I place an order for SPC5748CK1MMJ6R through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5748CK1MMJ6R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5748CK1MMJ6R reliable?
The price and inventory of SPC5748CK1MMJ6R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5748CK1MMJ6R is usually 5 days.
3.What payment methods are accepted for SPC5748CK1MMJ6R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5748CK1MMJ6R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5748CK1MMJ6R?
SPC5748CK1MMJ6R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5748CK1MMJ6R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5748CK1MMJ6R?
For technical support, including SPC5748CK1MMJ6R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5748CK1MMJ6R requirements.
6.How does Aetrix verify that SPC5748CK1MMJ6R is sourced from the original manufacturer or authorized distributors?
All SPC5748CK1MMJ6R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5748CK1MMJ6R meets industry standards.
7.What is the process for return or replacement of SPC5748CK1MMJ6R?
All SPC5748CK1MMJ6R units undergo pre-shipment inspection (PSI). If there is an issue with SPC5748CK1MMJ6R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5748CK1MMJ6R part is unused and in its original packaging.
Return procedure for SPC5748CK1MMJ6R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SPC5748CK1MMJ6R Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

