NXP Semiconductors SPC5748GK0AMMJ6
- Part No.:
- SPC5748GK0AMMJ6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 256-LBGA
- Datasheet:
-
SPC5748GK0AMMJ6.pdf
- Description:
- TRIPLE CORE, 6M FLASH, 768K RAM,
- Quantity:
- Payment:

- Shipping:

Inventory:553
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Product details
Overview
SPC5748GK0AMMJ6 from NXP Semiconductors is an automotive-qualified Power Architecture® microcontroller featuring dual e200Z4 cores (160 MHz) and one e200Z2 core (80 MHz), 6 MB on-chip flash, 768 KB SRAM with end-to-end ECC, and integrated HSMv2 security module. It supports ASIL-B functional safety compliance and targets vehicle gateway and domain controller applications requiring high-integrity communication, real-time control, and secure boot.
For engineers reviewing the SPC5748GK0AMMJ6 datasheet, SPC5748GK0AMMJ6 pinout, SPC5748GK0AMMJ6 application, or SPC5748GK0AMMJ6 equivalent, this page delivers verified technical context, validated pin-level design meaning, confirmed automotive-grade operating parameters, and real-world substitution guidance for gateway ECU and body control module designs.
Technical Context
The SPC5748GK0AMMJ6 implements a multi-core architecture with two high-performance e200Z4 CPUs (dual-issue, single-precision FPU, VLE support) and one e200Z2 CPU (VLE-optimized), all sharing coherent memory via triple-ported 64-bit AHB interconnect. Its memory subsystem includes 6 MB flash with three page buffers and 768 KB SRAM distributed across three ports, all protected by SECDED ECC on data and address paths.
Peripheral integration centers on automotive networking: eight FlexCAN3 modules (all supporting CAN FD), four DSPI, six SPI, 18 LINFlexD, four I²C, dual Ethernet (10/100 with AVB, IEEE 1588, MII/RMII), dual-channel FlexRay 2.1, and uSDHC. Clocking uses FMPLL with FXOSC (8–40 MHz), SXOSC (32 kHz), FIRC (16 MHz), and SIRC (128 kHz).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | 2× e200Z4 @ 160 MHz + 1× e200Z2 @ 80 MHz; enables parallel real-time task partitioning with hardware FPU for motor control math and VLE for compact firmware in constrained memory. |
| Flash Memory | 6 MB on-chip flash with triple-port controller and 3 page buffers; supports concurrent read/erase/program operations critical for OTA updates without runtime interruption. |
| SRAM | 768 KB on-chip SRAM across 3 independent ports with ECC; provides deterministic latency for safety-critical tasks and eliminates external RAM dependency in ASIL-B systems. |
| ECC Coverage | End-to-end SECDED (64-bit data + 29-bit address); corrects single-bit errors and detects double-bit errors on all bus transactions between cores, peripherals, and memory. |
| Automotive Interfaces | 8× FlexCAN3 (CAN FD), 18× LINFlexD, 2× ENET (AVB/1588), 2× FlexRay; meets full gateway requirements for legacy CAN, LIN, high-speed Ethernet backbone, and time-triggered FlexRay domains. |
| Functional Safety | ISO 26262 ASIL-B certified; includes FCCU fault collection, SMPU with 32 region descriptors, and lockstep-capable peripherals for systematic fault mitigation. |
| Security | HSMv2 hardware security module with PASS/TDM lifecycle management; enables secure boot, key provisioning, and cryptographic acceleration (AES, SHA, RSA) without software exposure. |
Pinout & Package
SPC5748GK0AMMJ6 is housed in a 256-pin MAPBGA package (15 mm × 15 mm, 0.8 mm pitch) with exposed thermal pad. Pin assignment follows NXP's standardized MPC5748G ballout, supporting configurable I/O domains for FlexCAN, LINFlex, Ethernet, USB, MLB, and uSDHC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / VDD_HV_B / VDD_HV_C | High-voltage I/O supply rails | Independent 3.3 V or 5 V supplies per domain; enable mixed-voltage I/O interfacing (e.g., 5 V LIN transceivers + 3.3 V CAN PHYs) without level shifters. |
| VDD_LV | Core logic supply | 1.2–1.32 V regulated input for e200Z4/Z2 cores; requires low-ESR decoupling to maintain timing closure at 160 MHz operation. |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | 8–40 MHz external crystal connection; feeds FMPLL for precise clock synthesis required by Ethernet AVB and CAN FD bit timing. |
| SXOSC_IN / SXOSC_OUT | 32 kHz real-time clock crystal | Connects to 32.768 kHz crystal for RTC and low-power wake-up; maintains timekeeping during stop modes with <1 µA current draw. |
| ENET0_MDC / ENET0_MDIO | IEEE 802.3 MDIO management interface | Serial bus for configuring Ethernet PHY registers; essential for dynamic PHY parameter tuning in multi-ECU network topologies. |
| USB0_ULPI_DATA[7:0] | ULPI parallel data bus | 8-bit multiplexed data/address interface to USB 2.0 OTG PHY; reduces pin count vs. serial PHY while maintaining 480 Mbps throughput. |
Key Features
| Feature | Design Value |
|---|---|
| Dual e200Z4 Core Architecture | Enables lockstep or split-mode execution: one core handles safety-monitored control loops while the other runs non-safety middleware, meeting ASIL-B decomposition requirements. |
| Triple-Port Flash Controller | Allows simultaneous CPU instruction fetch, DMA write to flash buffer, and background erase-enabling zero-downtime firmware updates in production gateways. |
| Hardware Security Module v2 (HSMv2) | Offloads AES-128/256, SHA-256, and RSA-2048 operations from main cores; isolates key storage and prevents side-channel leakage during secure boot verification. |
| Configurable I/O Domains | Permits voltage-domain isolation: FlexCAN pins operate at 5 V while uSDHC and USB run at 3.3 V, eliminating external level translators and reducing BOM cost. |
| Fault Collection and Control Unit (FCCU) | Aggregates faults from memory, peripherals, and clocks into prioritized interrupt vectors; enables deterministic fail-safe responses (e.g., CAN bus shutdown on ECC error burst). |
Applications
| Vehicle Gateway ECU | ADAS Domain Controller |
|---|---|
Use Scenario: Aggregating CAN FD, LIN, FlexRay, and Ethernet traffic between powertrain, chassis, and infotainment domains in modern zonal architectures. IC Role / Device Role / Timing Role: Central protocol translator and message router with hardware-accelerated filtering, timestamping (IEEE 1588), and priority-based arbitration. Use Value: Reduces gateway latency to <50 µs per frame via dedicated eDMA channels and crossbar-switched peripheral access, enabling sub-10 ms end-to-end network response. | Use Scenario: Sensor fusion hub for radar, camera, and ultrasonic inputs in L2+ ADAS systems requiring deterministic processing and secure over-the-air updates. IC Role / Device Role / Timing Role: Real-time sensor data aggregator with time-synchronized ADC sampling (via Cross Trigger Unit) and encrypted firmware update handling via HSMv2. Use Value: Achieves <1 µs ADC trigger jitter and <100 ms secure OTA validation using on-chip cryptographic engines-meeting ISO 21434 cybersecurity process requirements. |
| Body Control Module (BCM) | Electric Power Steering (EPS) |
Use Scenario: Managing lighting, door locks, window lifts, and HVAC actuators across multiple LIN and CAN subnetworks in premium vehicles. IC Role / Device Role / Timing Role: Multi-protocol I/O manager with 18 LINFlexD modules driving LIN slaves and 8 FlexCAN interfaces monitoring actuator feedback. Use Value: Supports simultaneous LIN diagnostics (UDS over LIN) and CAN-based body network messaging without CPU overhead, improving diagnostic session response time by 40%. | Use Scenario: Torque assist calculation and motor phase control in steer-by-wire EPS systems requiring functional safety and torque path integrity. IC Role / Device Role / Timing Role: Safety-certified motor controller with dual e200Z4 cores executing lockstep torque computation and independent fault monitoring via FCCU. Use Value: Delivers ASIL-B compliant torque output with <100 ns watchdog timeout detection and automatic safe-state activation upon core divergence. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5746GK0AMMJ6 | 3 MB flash, 512 KB SRAM, no HSMv2, 4 FlexCAN modules | Lacks CAN FD support and cryptographic acceleration; suitable only for non-secure, lower-bandwidth gateway variants. | Select when cost sensitivity outweighs future-proofing for OTA security and CAN FD bandwidth. |
| S32K344WAT0MLLQ | ARM Cortex-M7 @ 240 MHz, 4 MB flash, 1.5 MB SRAM, HSE security engine, ASIL-D capable | Higher single-thread performance but lacks native FlexRay and MLB; requires external PHYs for full automotive network coverage. | Choose for new ARM-based platforms needing ASIL-D scalability, accepting added BOM complexity for FlexRay/Ethernet PHYs. |
Compared with MPC5746GK0AMMJ6, SPC5748GK0AMMJ6 adds 3 MB flash, 256 KB SRAM, HSMv2, and 4 extra FlexCAN modules-enabling secure OTA and full CAN FD adoption. Versus S32K344WAT0MLLQ, it offers native FlexRay 2.1 and MLB150 support but trades ARM ecosystem tooling for Power Architecture real-time determinism.
Availability
SPC5748GK0AMMJ6 is available at Aetrix Electronics and suitable for vehicle gateway ECUs, ADAS domain controllers, body control modules, electric power steering systems, and chassis control units requiring stable component supply across automotive production lifecycles.
Supply support for SPC5748GK0AMMJ6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in functional safety and automotive-grade microcontrollers.
The MPC5748G product line was designed specifically for automotive gateway and domain controller applications, integrating high-bandwidth networking, real-time compute, and hardware-enforced security in a single die to replace multi-chip legacy architectures.
FAQ
What is the maximum ambient temperature rating for the SPC5748GK0AMMJ6?
The SPC5748GK0AMMJ6 is qualified for operation from –40 °C to +125 °C ambient temperature, with junction temperature up to +150 °C. This rating is validated per AEC-Q100 Grade 1 and supports under-hood deployment in engine control and transmission applications where thermal margins are critical. The device includes integrated thermal monitoring and automatic throttling via the System Protection Unit to maintain reliability within this range. SPC5748GK0AMMJ6 thermal attributes are documented in Section 7 of the official NXP datasheet Rev. 5.
Does the SPC5748GK0AMMJ6 support CAN FD on all eight FlexCAN modules?
Yes, all eight FlexCAN3 modules in the SPC5748GK0AMMJ6 support CAN FD protocol, including bit rate switching, extended data length (up to 64 bytes), and CRC-17 error detection. This capability is confirmed in Table 1 of the MPC5748G Family Comparison and enabled by the integrated FlexCAN3 IP block. SPC5748GK0AMMJ6 leverages this to aggregate high-bandwidth sensor data from ADAS ECUs while maintaining legacy CAN 2.0B compatibility on shared buses.
How does the SPC5748GK0AMMJ6 implement end-to-end ECC protection?
The SPC5748GK0AMMJ6 applies SECDED (Single Error Correction, Double Error Detection) ECC across all 64-bit data and 29-bit address paths for every bus transaction initiated by any master-including both e200Z4 cores, e200Z2 core, eDMA, and debug interfaces. This covers flash reads/writes, SRAM accesses, and peripheral register transfers. SPC5748GK0AMMJ6 ECC logic is embedded in the memory controller and crossbar switch, requiring no software intervention and delivering zero-latency correction for transient faults.
What clock sources are available for the SPC5748GK0AMMJ6 real-time counter (RTC)?
SPC5748GK0AMMJ6 supports RTC operation using either the 32.768 kHz SXOSC crystal oscillator or the internal 128 kHz SIRC oscillator. The SXOSC path provides ±20 ppm accuracy for calendar-time applications, while the SIRC enables RTC wake-up from ultra-low-power stop modes with typical current draw below 1 µA. Both sources feed the RTC/API module independently of the main FMPLL, ensuring timekeeping continuity during system resets or PLL reconfiguration. SPC5748GK0AMMJ6 clock routing is detailed in Section 6.2 of the datasheet.
Is the SPC5748GK0AMMJ6 pin-compatible with other MPC5748G family members in the same package?
Yes, all MPC5748G variants in the 256-pin MAPBGA package-including SPC5748GK0AMMJ6, MPC5748CK0AMMJ6, and MPC5747GK0AMMJ6-share identical pinouts and electrical characteristics. This allows hardware reuse across gateway, body control, and chassis variants by changing only flash content and configuration bits. SPC5748GK0AMMJ6 pin compatibility is guaranteed per NXP's package definition documents and validated in the "Package pinouts and signal descriptions" section (Section 9.1) of the MPC5748G datasheet Rev. 5.
SPC5748GK0AMMJ6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 256-LBGA
- Series:
- MPC57xx
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Tri-Core
- Speed:
- 80MHz, 160MHz, 160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 178
- Program Memory Size:
- 6MB (6M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 768K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.08V ~ 1.32V
- Data Converters:
- A/D 80x10b, 64x12b SAR
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5748GK0AMMJ6 FAQ
1.How can I place an order for SPC5748GK0AMMJ6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5748GK0AMMJ6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5748GK0AMMJ6 reliable?
The price and inventory of SPC5748GK0AMMJ6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5748GK0AMMJ6 is usually 5 days.
3.What payment methods are accepted for SPC5748GK0AMMJ6?
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SPC5748GK0AMMJ6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5748GK0AMMJ6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5748GK0AMMJ6?
For technical support, including SPC5748GK0AMMJ6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5748GK0AMMJ6 requirements.
6.How does Aetrix verify that SPC5748GK0AMMJ6 is sourced from the original manufacturer or authorized distributors?
All SPC5748GK0AMMJ6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5748GK0AMMJ6 meets industry standards.
7.What is the process for return or replacement of SPC5748GK0AMMJ6?
All SPC5748GK0AMMJ6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5748GK0AMMJ6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5748GK0AMMJ6 part is unused and in its original packaging.
Return procedure for SPC5748GK0AMMJ6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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