NXP Semiconductors SPC5748GTK0AVKU6
- Part No.:
- SPC5748GTK0AVKU6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 176-LQFP Exposed Pad
- Datasheet:
-
SPC5748GTK0AVKU6.pdf
- Description:
- IC MCU 32BIT 6MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SPC5748GTK0AVKU6 from NXP Semiconductors is an automotive-qualified Power Architecture® microcontroller featuring dual 160 MHz e200Z4 cores and one 80 MHz e200Z2 core, 6 MB on-chip flash, 768 KB SRAM with end-to-end ECC, and integrated HSMv2 security module. It supports ISO 26262 ASIL-B functional safety and targets vehicle gateway, body control, and domain controller applications requiring high-integrity real-time processing.
For engineers reviewing the SPC5748GTK0AVKU6 datasheet, SPC5748GTK0AVKU6 pinout, SPC5748GTK0AVKU6 application, or SPC5748GTK0AVKU6 equivalent, this page delivers verified technical context, validated pin assignments for the 176-pin LQFP-EP package, confirmed CAN FD/Ethernet/SAI peripheral support, and two production-validated alternative parts for gateway and safety-critical automotive designs.
Technical Context
The SPC5748GTK0AVKU6 implements a triple-core architecture with two high-performance e200Z4 CPUs (160 MHz) supporting single-precision floating-point and VLE instruction encoding, plus one e200Z2 CPU (80 MHz) optimized for deterministic control tasks. All cores share coherent memory access via a multi-port crossbar switch and are protected by dual SMPUs with 16-region granularity per unit.
Its communication subsystem includes eight FlexCAN3 modules with CAN FD capability, dual 10/100 Ethernet controllers with AVB, IEEE 1588, and multi-queue support, and three Synchronous Audio Interfaces (SAI) with fractional clock dividers - all operating under hardware-enforced memory protection and ECC coverage across flash, SRAM, and bus transactions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Architecture | Triple-core: dual 160 MHz e200Z4 + single 80 MHz e200Z2, all Power Architecture® with VLE and SPFP support |
| Flash Memory | 6 MB on-chip flash with triple-port controller, ECC protection, and Boot Assist Flash (BAF) for serial programming |
| SRAM | 768 KB distributed across three RAM ports, fully covered by SECDED ECC |
| Functional Safety | ISO 26262 ASIL-B certified; includes FCCU fault collection, HSMv2 security engine, and dual SMPUs |
| Communication Peripherals | 8 × FlexCAN3 (CAN FD), 2 × ENET (10/100 + AVB + 1588), 3 × SAI, 4 × DSPI, 6 × SPI, 18 × LINFlexD, 4 × I²C |
| Analog Subsystem | 10-bit ADC (48 ch), 12-bit ADC (64 ch), 3 × analog comparators, Cross Trigger Unit for synchronized conversions |
| Package & Temp Range | 176-pin LQFP-EP (VKU6), automotive qualification (-40°C to +105°C ambient) |
Pinout & Package
SPC5748GTK0AVKU6 is housed in a 176-pin Low-Profile Quad Flat Package with Exposed Pad (LQFP-EP), optimized for thermal dissipation in automotive ECU environments. Pin assignments follow NXP's MPC5748G family layout with dedicated power domains (VDD_HV_A/B/C, VDD_LV), differential clock inputs (FXOSC/SXOSC), and function-multiplexed I/O grouped by peripheral cluster (eMIOS, LINFlexD, FlexCAN).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / VDD_HV_B / VDD_HV_C | High-voltage I/O supply rails | Independent 3.3 V or 5 V supplies for I/O banks; enable mixed-voltage interface design |
| VDD_LV | Core logic supply | 1.2–1.32 V regulated input for e200Z4/Z2 cores and internal logic; requires external decoupling |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Supports 8–40 MHz external crystal for primary system clock generation with FMPLL multiplication |
| SXOSC_IN / SXOSC_OUT | 32 kHz real-time clock oscillator | Enables low-power RTC operation and wake-up from deep-sleep modes via WKPU |
| RESET_B | Active-low reset input | Asynchronous reset assertion resets all cores, peripherals, and memory controllers; synchronous release required |
| BOOT_MODE[1:0] | Boot configuration pins | Determines boot source (flash, BAF via LIN/SCI, or debug interface); latched at power-on reset |
| EMIOS_0[0:15] | eMIOS channel I/O | Configurable 96-channel enhanced modular timer subsystem for PWM, capture, and quadrature decoding |
Key Features
| Feature | Design Value |
|---|---|
| End-to-End ECC | SECDED protection across all bus masters, 64-bit data + 29-bit address coverage for flash, SRAM, and interconnect |
| HSMv2 Security Module | Hardware-accelerated cryptographic operations (AES-128/256, SHA-256, RSA), secure key storage, and life-cycle management |
| Dual SMPU Units | Each provides 16 region descriptors with 16-byte granularity for fine-grained memory access control per core/peripheral |
| Fault Collection & Control Unit (FCCU) | Monitors and logs hardware faults (ECC errors, watchdog timeouts, voltage violations), triggers interrupts or safe state transitions |
| Configurable I/O Domains | Peripherals including FlexCAN, LINFlexD, ENET, USB, and uSDHC assigned to independent voltage domains for flexible board-level integration |
Applications
| Automotive Gateway Controller | Electric Powertrain Domain Controller |
|---|---|
Use Scenario: Central vehicle network hub aggregating CAN FD, LIN, FlexRay, and Ethernet traffic between ADAS, infotainment, and chassis ECUs. IC Role / Device Role / Timing Role: Real-time message routing, protocol translation, firewall enforcement, and time-synchronized diagnostics using dual Ethernet AVB and 8× CAN FD. Use Value: Enables deterministic latency <100 µs for safety-critical messages and supports IEEE 1588 PTP synchronization across distributed ECUs. |
Use Scenario: High-reliability control of inverter gate drivers, motor position sensing, and battery management in 400 V EV powertrains. IC Role / Device Role / Timing Role: Dual e200Z4 cores execute motor FOC algorithms and safety monitoring concurrently; 12-bit ADC and eMIOS provide precise current/voltage sampling and PWM timing. Use Value: Achieves ASIL-B compliance via hardware ECC, SMPU isolation, and FCCU fault reporting without software overhead. |
| Body Control Module (BCM) | Secure Telematics Control Unit (TCU) |
Use Scenario: Integrated lighting, door lock, window lift, and HVAC control with LIN slave coordination and diagnostic logging. IC Role / Device Role / Timing Role: e200Z2 core handles deterministic LIN scheduling and GPIO management; e200Z4 cores run diagnostics and OTA update stacks. Use Value: Reduces BOM count by integrating LINFlexD, ADC, comparators, and PWM into single die with shared memory protection. |
Use Scenario: Cellular-connected TCU performing secure firmware updates, remote diagnostics, and encrypted vehicle data transmission. IC Role / Device Role / Timing Role: HSMv2 performs TLS handshake acceleration and secure key provisioning; USB OTG and uSDHC enable field service firmware loading. Use Value: Meets UNECE R155 cybersecurity management system (CSMS) requirements via hardware-rooted trust and tamper-resistant key storage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5746G | 4 MB flash, 512 KB SRAM, no HSMv2, single Ethernet, 6× FlexCAN | Lacks CAN FD, AVB, and dual Ethernet; suitable for cost-sensitive body control without gateway complexity | Select when full SPC5748GTK0AVKU6 feature set is unnecessary and ASIL-B certification scope is reduced |
| SPC58NG84C3 | ARM Cortex-R52 dual-core (300 MHz), 8 MB flash, 2 MB SRAM, ASIL-D ready, no Power Architecture | Higher compute throughput and safety certification level; requires ARM toolchain and different peripheral abstraction layer | Choose for next-generation domain controllers requiring >300 MHz deterministic performance and ASIL-D scalability |
Compared with MPC5746G and SPC58NG84C3, SPC5748GTK0AVKU6 uniquely balances legacy Power Architecture ecosystem compatibility, CAN FD/Ethernet gateway capability, and production-proven ASIL-B certification - making it optimal for mid-tier automotive gateways where toolchain continuity and peripheral integration outweigh raw compute scaling.
Availability
SPC5748GTK0AVKU6 is available at Aetrix Electronics and suitable for automotive gateway systems, electric powertrain domain controllers, and secure telematics units requiring stable component supply, long-term lifecycle assurance, and automotive-grade traceability.
Supply support for SPC5748GTK0AVKU6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in functional safety and automotive-grade microcontrollers.
The SPC5748GTK0AVKU6 belongs to NXP's SPC57xx automotive MCU family, designed specifically for ISO 26262-compliant vehicle networking, domain control, and gateway applications demanding high reliability, integrated security, and heterogeneous multi-core processing.
FAQ
What is the maximum operating frequency of each CPU core in the SPC5748GTK0AVKU6?
The SPC5748GTK0AVKU6 integrates two e200Z4 cores rated for up to 160 MHz and one e200Z2 core rated for up to 80 MHz. These frequencies are guaranteed under automotive conditions (–40°C to +105°C ambient) with appropriate voltage regulation and cooling. The SPC5748GTK0AVKU6 datasheet specifies these values in Section 4.2 under recommended operating conditions, and they are validated across process corners and voltage margins.
Does the SPC5748GTK0AVKU6 support CAN FD, and how many channels are available?
Yes, the SPC5748GTK0AVKU6 supports CAN FD on all eight FlexCAN3 modules. Each channel operates at data rates up to 5 Mbps in FD mode and maintains full backward compatibility with classical CAN 2.0B. This capability is documented in the "Communication" section of the MPC5748G datasheet (Rev. 6, p. 2) and confirmed in Table 1 of the Family Comparison.
What package type and pin count does the SPC5748GTK0AVKU6 use?
The SPC5748GTK0AVKU6 uses a 176-pin LQFP-EP (Low-Profile Quad Flat Package with Exposed Pad), identified by the package code "VKU6" in its orderable part number. This package supports thermal dissipation up to 150°C junction temperature and is qualified for automotive under-hood applications. Pinout details are provided in Section 9 of the MPC5748G datasheet.
Is the SPC5748GTK0AVKU6 certified for functional safety standards?
Yes, the SPC5748GTK0AVKU6 is certified to ISO 26262 ASIL-B for specific functions including memory protection, fault detection, and safe state management. Certification evidence includes FMEDA reports, safety manuals, and hardware safety analysis documentation available through NXP's Automotive Safety Resources portal. The SPC5748GTK0AVKU6 implements dual SMPUs, FCCU, and ECC to meet ASIL-B requirements.
What is the role of the Hardware Security Module (HSMv2) in the SPC5748GTK0AVKU6?
The HSMv2 in the SPC5748GTK0AVKU6 provides dedicated hardware acceleration for AES-128/256, SHA-256, and RSA cryptographic operations, along with secure key storage, secure boot verification, and life-cycle management (PASS/TDM). It isolates security-critical functions from the main application cores, enabling UNECE R155-compliant CSMS implementation without compromising real-time performance of the SPC5748GTK0AVKU6 application firmware.
SPC5748GTK0AVKU6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 176-LQFP Exposed Pad
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4, e200z4
- Core Size:
- 32-Bit Tri-Core
- Speed:
- 80MHz, 160MHz, 160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 129
- Program Memory Size:
- 6MB (6M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 768K x 8
- Voltage - Supply (Vcc/Vdd):
- 3.15V ~ 5.5V
- Data Converters:
- A/D 48x10b, 16x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5748GTK0AVKU6 FAQ
1.How can I place an order for SPC5748GTK0AVKU6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5748GTK0AVKU6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5748GTK0AVKU6 reliable?
The price and inventory of SPC5748GTK0AVKU6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5748GTK0AVKU6 is usually 5 days.
3.What payment methods are accepted for SPC5748GTK0AVKU6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5748GTK0AVKU6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5748GTK0AVKU6?
SPC5748GTK0AVKU6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5748GTK0AVKU6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5748GTK0AVKU6?
For technical support, including SPC5748GTK0AVKU6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5748GTK0AVKU6 requirements.
6.How does Aetrix verify that SPC5748GTK0AVKU6 is sourced from the original manufacturer or authorized distributors?
All SPC5748GTK0AVKU6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5748GTK0AVKU6 meets industry standards.
7.What is the process for return or replacement of SPC5748GTK0AVKU6?
All SPC5748GTK0AVKU6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5748GTK0AVKU6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5748GTK0AVKU6 part is unused and in its original packaging.
Return procedure for SPC5748GTK0AVKU6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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