STMicroelectronics SR1UARU

Overview

SR1UARU from STMicroelectronics is a Smart Reset™ supervisory IC with fixed 10.0 s extended setup delay (tSRC), active-low open-drain reset output (RST), and active-low Smart Reset input (SR) without internal pull-up. It operates from 2.0 V to 5.5 V, draws only 1 µA typical supply current, and is housed in a 1.00 mm × 1.45 mm UDFN6 package. Designed for wearable electronics, it enables reliable push-button-initiated hard resets while rejecting short glitches.

For engineers reviewing the SR1UARU datasheet, SR1UARU pinout, SR1UARU application, or SR1UARU equivalent, this device supports voltage-domain-flexible reset control in compact wearables-where precise tSRC timing, ultra-low ICC, and test-mode diagnostics are critical selection criteria.

Technical Context

The SR1UARU implements a factory-programmed 10.0 s Smart Reset delay (tSRC) before asserting RST, with no minimum or fixed reset pulse width (tREC = not programmed). Its logic detects SR low for ≥10 s to trigger an active-low RST output that remains asserted only while SR stays low-enabling software-interrupt vs. hardware-reset differentiation.

Test mode entry requires SR > VCC + 1.1 V (typ.), initiating a 42 ms initial counter (tSRC-INI); subsequent SR ground pulses shorten delay to tSRC/128 (~78 ms). The device guarantees high-Z RST during undervoltage and supports safe power-up sequencing across mixed-voltage domains.

Key Specifications

Pinout & Package

SR1UARU is packaged in a 6-pin UDFN (1.00 mm × 1.45 mm, 0.50 mm pitch), RoHS-compliant and halogen-free per ECOPACK®2. Pins 5 and 6 are not bonded and must be connected to VSS for mechanical stability and thermal performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Smart Reset supervisory applications.

Compared with MAX6326UR29+T and TPS3808G12DBVR, SR1UARU uniquely delivers factory-programmed 10 s delay, 1 µA ICC, and UDFN6 size-making it optimal for space- and power-constrained wearable reset control where timing precision and zero external components are critical.

Availability

SR1UARU is available at Aetrix Electronics and suitable for wearable fitness trackers, smartwatches, smartglasses, and activity monitors requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.

Supply support for SR1UARU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, delivering intelligent power, sensing, and control solutions for automotive, industrial, and consumer markets.

SR1UARU belongs to ST's Smart Reset™ family-designed specifically for ultra-low-power, push-button-initiated system recovery in compact portable electronics where traditional reset ICs lack timing intelligence and glitch immunity.

FAQ

What is the exact tSRC value for SR1UARU, and is it adjustable?

The SR1UARU has a factory-programmed Smart Reset delay (tSRC) of exactly 10.0 seconds (typical), with ±20% variation over −40 °C to +85 °C. This value is laser-trimmed during production and cannot be adjusted in-circuit or via external components-it is fixed and guaranteed per the datasheet's Table 4.

Does SR1UARU include an internal pull-up resistor on the SR input?

No. SR1UARU (suffix "A" in ordering code) features an active-low SR input with no internal pull-up resistor. An external pull-up resistor is required to ensure the SR pin defaults to logic high when the push-button is open-preventing spurious resets due to floating input.

Can SR1UARU drive a microcontroller's active-high reset pin directly?

No. SR1UARU provides only active-low open-drain RST output. To interface with an active-high reset input, an external pull-down resistor is required on the MCU side-or a discrete inverter. The device does not support active-high push-pull output in the UARU variant.

How is test mode triggered, and what happens once entered?

Test mode is triggered by applying >VCC + 1.1 V to the SR pin, causing RST to assert after ~42 ms (tSRC-INI). Subsequent grounding of SR shortens delay to tSRC/128 (~78 ms). Normal operation resumes only after full VCC power cycle-no software command or pin sequence exits test mode.