STMicroelectronics SRC0GS22D

Overview

SRC0GS22D from STMicroelectronics is a smart push-button on/off controller with Smart Reset™ and power-on lockout, designed for ultra-low-power wearable systems. It operates from 1.6 V to 5.5 V, draws only 0.6 µA in standby, features a precise 1.5 V ±1% voltage reference, and supports debounced PB/SR inputs with ±15 kV air-discharge ESD protection. It controls system power via an active-high or active-low enable output (EN/EN) driving MOSFETs or DC-DC converters in activity trackers and smartwatches.

For engineers reviewing the SRC0GS22D datasheet, SRC0GS22D pinout, SRC0GS22D application, or SRC0GS22D equivalent, key selection criteria include its adjustable Smart Reset™ delay (via CSRD capacitor), tON_BLANK power-up confirmation timing, PSHOLD-driven startup lockout, undervoltage detection with separate VCCLO output, and dual-mode long-push behavior (RST assertion or EN deassertion).

Technical Context

The SRC0GS22D implements a state-machine-based power sequencing controller that monitors PB and SR inputs for short/long press events while continuously validating VCC against factory-trimmed thresholds VTH+ (3.4 V typ.) and VTH– (3.2 V typ., 200 mV hysteresis). Its logic integrates edge detection, debounce (tDEBOUNCE = 15 ms typ.), and time-blanking windows (tON_BLANK = 250 ms typ.) to prevent false startups.

It delivers three independent outputs: EN/EN (push-pull, configurable polarity) for main power control; RST (open-drain, active-low, tREC = 200 ms typ.) for microcontroller reset; and INT (open-drain, active-low) asserting on either PB press or VCC undervoltage-distinguishable via PBOUT status. The VREF output provides a stable 1.5 V ±1% reference for external circuitry.

Key Specifications

Pinout & Package

Supplied in a space-constrained TDFN12 (2 mm × 3 mm, 0.5 mm pitch) package optimized for wearable PCB real estate.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar smart push-button controller applications.

Compared with TPS3808G33 and MAX16054, SRC0GS22D uniquely integrates push-button state machine, adjustable Smart Reset™, PSHOLD lockout, and precision VREF - enabling self-contained, ultra-low-power power control in wearables without firmware dependency.

Availability

SRC0GS22D is available at Aetrix Electronics and suitable for wearable electronics, activity trackers, and smartwatches requiring stable component supply, long-term lifecycle support, and guaranteed traceability for medical-grade or consumer-certified designs.

Supply support for SRC0GS22D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, delivering silicon solutions for automotive, industrial, and consumer markets with emphasis on energy efficiency and reliability.

The SRC0 product line targets ultra-low-power human-interface power management - specifically engineered to replace discrete button + reset + supervisor circuits in space- and battery-constrained wearables.

FAQ

What is the function of the PSHOLD pin and why is it required?

The PSHOLD pin enforces a hardware power-on lockout: after PB press, the host MCU must drive PSHOLD high within 250 ms (tON_BLANK) to sustain EN assertion. This prevents booting with unstable rails or unresponsive processors. During startup, an internal pull-down ensures PSHOLD defaults low unless actively driven - eliminating need for external components.

How does the CSRD capacitor affect Smart Reset™ behavior?

The CSRD capacitor sets the Smart Reset™ delay time (tSRD): charging at 1.2 µA against a 1.2 V threshold determines how long PB and SR must be held together to trigger reset or shutdown. For example, a 1.0 µF capacitor yields ~1 second tSRD. Leaving CSRD open disables tSRD, causing long-press recognition immediately after tINT_Min (15 ms).

Can SRC0GS22D drive a high-side PMOS directly, and what are the voltage limits?

Yes - the EN output is push-pull and rated for 5.5 V max, allowing direct drive of high-side PMOS gates (e.g., Si2301) without level-shifting. Output swing is rail-to-rail (0 V to VCC), with sink/source capability sufficient for typical PMOS gate capacitance (<1 nF). EN remains functional down to 1.6 V VCC, supporting deep battery discharge operation.

Is the 1.5 V VREF output mandatory to use, and what happens if left unconnected?

VREF requires a 1 µF capacitor to ground regardless of usage - this stabilizes the internal reference circuit and prevents oscillation or excessive current draw. Without it, VREF may become unstable, degrading accuracy of internal comparators and potentially causing erratic PB/SR detection or reset timing. The capacitor is mandatory per datasheet Section 2.3.