STMicroelectronics SRK1004ATR

Overview

SRK1004ATR from STMicroelectronics is a secondary-side synchronous rectification controller optimized for Non-Complementary Actively Clamped Flyback (NC-ACF) converters. It drives N-channel MOSFETs in both high-side and low-side configurations, supports logic-level and standard-level MOSFETs, features 25 ns typ. turn-off delay, operates up to 500 kHz, and delivers 580 µA operating current - enabling high-efficiency USB-PD wall-plug adapters.

For engineers reviewing the SRK1004ATR datasheet, SRK1004ATR pinout, SRK1004ATR application, or SRK1004ATR equivalent, key selection criteria include drain-sense voltage range (−1 to 160 V), internal 5.5 V regulated VCC, SCP pin short-circuit detection threshold (1 V reference), DVS pin noise-immune zero-current detection, and DFN 6L 2×2 mm thermal performance (R_thJ-BC = 19 °C/W).

Technical Context

The SRK1004ATR implements adaptive zero-current switching via high-voltage DVS sensing with −330 mV typ. turn-on threshold and 0 V typ. turn-off threshold, coupled with 25 ns internal extra turn-off delay to compensate for MOSFET stray inductance-induced timing advance. Its dual-mode operation supports NC-ACF, resonant flyback, and quasi-resonant topologies across CCM–DCM boundary and DCM load conditions.

It integrates a fast short-circuit detector using the SCP pin (1 V reference, 20 µA detection threshold) and provides two distinct turn-on enable windows (125 ns typ. for A/B/C/D variants) to reject false triggers during high-side switch transitions and DCM ringing - ensuring reliable SR MOSFET gating only during the T_DEM demagnetization interval.

Key Specifications

Pinout & Package

SRK1004ATR is housed in a thermally enhanced DFN 6L 2×2 mm package with exposed pad (EP) for PCB-level thermal dissipation. The EP must be connected to GND for optimal junction-to-board thermal resistance (19 °C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous rectification controller applications.

Compared with SRK1004BTR and UCC24612-2QDR, the SRK1004ATR offers topology-specific NC-ACF timing optimization, lower quiescent current (230 µA vs. 350 µA), and integrated SCP functionality - making it the preferred choice for consumer USB-PD adapters targeting CoC Tier 2 and ERP Lot 9 compliance.

Availability

SRK1004ATR is available at Aetrix Electronics and suitable for high-power-density USB-PD adapters/chargers, in-wall smart outlets, and resonant flyback power supplies requiring stable component supply and long-term production continuity.

Supply support for SRK1004ATR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, analog chips, and MEMS sensors for industrial, automotive, and consumer markets.

The SRK1004 product line targets high-efficiency AC/DC secondary-side synchronous rectification in advanced flyback topologies - specifically engineered to maximize power density and minimize no-load consumption in USB-PD and smart outlet applications.

FAQ

What is the recommended DVS pin series resistor value and type?

A 220 Ω thick-film 0805 SMD resistor is mandatory between DVS and the SR MOSFET drain to limit dynamic current injection and ensure ESD robustness. For high-stress applications with frequent short-circuit events, two 0603 resistors in series provide better power dissipation margin and voltage rating headroom.

Can SRK1004ATR operate in high-side configuration without an auxiliary winding?

No - in high-side configuration, the VO pin must be powered from a floating auxiliary winding with rectifying diode and buffer capacitor. Direct connection to output voltage would violate isolation requirements and cause functional failure due to common-mode voltage mismatch.

How does the SCP pin function differ between low-side and high-side configurations?

In high-side configuration, the SCP pin enables output short-circuit protection by setting a ~3 V trip threshold via external resistor. In low-side configuration, SCP protection is disabled by connecting a 22 kΩ resistor to GND, and protection relies solely on VO UVLO (turn-off at 4.0 V).

What is the minimum required VCC bypass capacitance and placement rule?

A 100 nF ceramic capacitor must be placed directly between VCC and GND, with traces shorter than 2 mm and via-in-pad grounding to minimize loop inductance. This ensures clean gate-driver supply during 1.5 A sink pulses and prevents false triggering from supply droop during high-frequency switching.