STMicroelectronics SRK1004DTR

Overview

SRK1004DTR from STMicroelectronics is a secondary-side synchronous rectification controller optimized for Non-Complementary Actively Clamped Flyback (NC-ACF) converters, supporting high-side and low-side configurations with 9.0 V internally regulated VCC, 150 ns typ. turn-off delay, and 125 ns typ. turn-on enable window. It drives N-channel MOSFETs in USB-PD wall-plug adapters operating up to 500 kHz with 190 V AMR drain-sense capability.

For engineers reviewing the SRK1004DTR datasheet, SRK1004DTR pinout, SRK1004DTR application, or SRK1004DTR equivalent, key selection factors include its dual-configurability (high/low-side), logic/standard-level MOSFET support, 580 µA operating current, 190 V DVS rating, and NC-ACF-specific timing control for zero-current switching accuracy.

Technical Context

The SRK1004DTR implements a voltage-mode sensing architecture that detects SR MOSFET drain-source voltage (DVS) transitions to trigger gate drive (GD) with precise timing: turn-on occurs when DVS falls below −330 mV (typ), and turn-off is initiated near zero-crossing with 150 ns internal extra delay to compensate for stray inductance-induced timing advance. Its dual-mode operation supports both CCM-DCM boundary and DCM flyback topologies.

It integrates a 9.0 V linear regulator (VCC) powered from VO (4–36 V), delivers 0.6 A peak source / 1.7 A peak sink gate drive, and features fast short-circuit detection via SCP pin with 1 V reference-enabling output voltage monitoring down to 3 V in high-side configuration. The device enters ultra-low-power burst mode (<230 µA quiescent) during primary-side idle intervals.

Key Specifications

Pinout & Package

SRK1004DTR uses a thermally enhanced DFN-6L (2 × 2 mm, 0.5 mm pitch) package with exposed pad (EP) connected to GND for low thermal resistance (R_thJ-BC = 19 °C/W). Pin layout is optimized for minimal loop area between GD, DVS, and GND to suppress noise-induced false triggering.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous rectifier controller applications.

Compared with SRK1004CTR and SRK1004BTR, the SRK1004DTR uniquely balances 9.0 V VCC headroom for direct V_OUT powering in high-voltage USB-PD designs with 150 ns turn-off delay optimized for mid-range GaN/Si MOSFETs-making it the preferred choice for 45–100 W NC-ACF adapters where layout parasitics vary across production batches.

Availability

SRK1004DTR is available at Aetrix Electronics and suitable for high-power-density USB-PD adapters/chargers, in-wall smart outlets, and universal travel adapters requiring stable component supply, consistent parametric performance, and long-term lifecycle support.

Supply support for SRK1004DTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.

The SRK1004 product line targets high-efficiency AC-DC conversion in compact power supplies, specifically engineered to replace secondary-side diodes in NC-ACF, resonant flyback, and quasi-resonant topologies with precise, adaptive synchronous rectification.

FAQ

Can SRK1004DTR be used in quasi-resonant flyback converters?

Yes. The SRK1004DTR is explicitly qualified for quasi-resonant flyback operation per its datasheet description and timing architecture. Its DVS sensing, 125 ns turn-on enable window, and blanking times (TON_MIN = 530 ns, TOFF_MIN = 270 ns) are designed to reliably detect valley-switching events and avoid false triggering during resonant ringing-enabling >93% efficiency at 65 W with standard QR controllers.

What is the minimum recommended DVS series resistor value and why?

The datasheet specifies a minimum 220 Ω thick-film 0805 SMD resistor between DVS pin and SR MOSFET drain. This value limits dynamic current injection during fast dV/dt transients (e.g., during TREV ringing), prevents latch-up in the high-voltage comparator input, and ensures ESD robustness (±2 kV HBM). Using <220 Ω risks exceeding the DVS pin's ±1.7 mA current rating during 190 V transients.

How does the SCP pin function differ between high-side and low-side configurations?

In high-side configuration, SCP sets output short-circuit protection: a 200 kΩ resistor from SCP to GND creates a ~3 V threshold-SRK1004DTR disables GD when V_OUT drops below this level. In low-side configuration, SCP protection is inactive; instead, UVLO on VO (V_OOff = 4.0 V) disables the IC if output voltage collapses, ensuring fail-safe shutdown without external components.

Is an external bootstrap capacitor required for high-side operation?

No. The SRK1004DTR does not require a bootstrap capacitor. In high-side configuration, it is powered from a dedicated floating auxiliary winding (rectified and buffered), with VO connected to that rail. The internal LDO generates stable 9.0 V VCC regardless of VO ripple-eliminating bootstrapping complexity and enabling reliable start-up even with slow-rising auxiliary voltages.