STMicroelectronics SRK2000ATR
- Part No.:
- SRK2000ATR
- Manufacturer:
- STMicroelectronics
- Category:
- Power Supply Controllers, Monitors
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SRK2000ATR.pdf
- Description:
- IC SMART DVR SYNC RECT LLC 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,549
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Product details
Overview
SRK2000ATR from STMicroelectronics is a synchronous rectifier smart driver IC optimized for secondary-side control in LLC resonant converters with center-tapped transformer windings. It features dual N-channel MOSFET gate drivers (1 A source / 3.5 A sink), matched turn-off thresholds (±1 mV), intelligent automatic sleep mode (250 µA quiescent current), and operates from 4.5–32 V at up to 500 kHz - deployed in high-efficiency 90+/92+ server SMPS.
For engineers reviewing the SRK2000ATR datasheet, SRK2000ATR pinout, SRK2000ATR application, or SRK2000ATR equivalent, key selection criteria include drain-sensing threshold matching, interlocked dual-gate drive timing, UVLO programmability via EN pin, and light-load sleep-mode exit behavior under load transients.
Technical Context
The SRK2000ATR implements a cycle-by-cycle, interlocked dual-state-machine control architecture that senses drain voltage polarity and magnitude on DVS1/DVS2 to trigger gate drive with precise timing: turn-on occurs at –200 mV (body diode conduction onset), while turn-off is set via EN-biased thresholds of –12 mV or –25 mV with <1 mV matching between channels.
Its internal logic enforces strict dead-time enforcement - preventing simultaneous conduction - and includes dedicated comparators for pre-triggering (0.7 V), arming (1.4 V), and current-reversal protection (zero-reference comparator active in first half-cycle). Sleep mode activation is determined by sustained low VCC-derived EN voltage, reducing Iq to 150 µA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Operating frequency | Up to 500 kHz - supports high-switching-frequency LLC topologies without timing degradation. |
| Gate drive strength | 1 A source / 3.5 A sink peak - ensures fast, robust turn-on/turn-off of paralleled N-MOSFETs in high-current SR stages. |
| Turn-off threshold matching | ±1 mV between DVS1/DVS2 - guarantees balanced current sharing and prevents cross-conduction-induced losses. |
| Quiescent current | 250 µA typical (active), 150 µA in sleep mode - directly improves light-load efficiency in ATX/server PSUs. |
| UVLO hysteresis | 0.25 V - provides stable startup/shutdown sequencing across input voltage variations in wide-range AC-DC adapters. |
| Drain sensing thresholds | –200 mV turn-on, –12/–25 mV selectable turn-off - enables precise zero-current switching detection for minimal conduction loss. |
| Supply voltage range | 4.5 V to 32 V - accommodates both low-voltage logic-level MOSFETs and higher-Vth power devices in diverse SMPS designs. |
Pinout & Package
SRK2000ATR is housed in an SO-8 package with exposed thermal pad (standard JEDEC MS-012AC), optimized for PCB heat dissipation in high-power density SMPS layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 SGND | Signal ground reference | 0 V reference for internal comparators and bias currents; must be routed directly to PGND plane to avoid sensing offset errors. |
| 2 EN | Threshold programming & enable input | Configures VDVS1/2 turn-off level (–12/–25 mV) and UVLO thresholds; pulling to GND disables GD1/GD2 outputs. |
| 3 DVS1 | Drain voltage sense channel 1 | Senses SR1 MOSFET drain; triggers turn-on at –200 mV and turn-off at EN-set threshold - requires series resistor for overvoltage clamping. |
| 4 DVS2 | Drain voltage sense channel 2 | Identical function to DVS1; matched internal thresholds ensure symmetrical timing for full-wave center-tap rectification. |
| 5 GD2 | Gate driver output 2 | Drives SR2 MOSFET gate with 1 A source / 3.5 A sink; clamped to ~12 V to prevent overdrive with high VCC. |
| 6 PGND | Power ground return | Return path for gate drive pulsed currents; must connect to common source node of both SR MOSFETs to minimize ground bounce. |
| 7 GD1 | Gate driver output 1 | Drives SR1 MOSFET gate with identical specs to GD2; interlocked with GD2 to prevent shoot-through. |
| 8 VCC | Supply voltage input | 4.5–32 V DC input; requires local 0.1 µF bypass to SGND and separate 0.1 µF to PGND for noise immunity and gate drive stability. |
Key Features
| Feature | Design Value |
|---|---|
| Intelligent automatic sleep mode | Detects sustained low-load condition via EN pin voltage decay and reduces Iq to 150 µA - eliminates SR losses where body-diode conduction becomes more efficient. |
| Interlocked dual gate drivers | Hardware-enforced mutual exclusion prevents GD1/GD2 overlap - eliminates shoot-through risk without external timing components or microcontroller coordination. |
| Matched turn-off thresholds | ≤1 mV mismatch between DVS1/DVS2 turn-off points - ensures equal conduction time and current sharing across both SR legs in center-tap topology. |
| Programmable UVLO with hysteresis | EN pin configures VCC turn-on (4.5 V) and turn-off (4.25 V) thresholds independently - enables clean start-up sequencing and brown-out recovery. |
| Drain-sensing noise immunity | 250 ns turn-on debounce and zero-crossing comparator for current reversal - rejects EMI-induced false triggering during high-dV/dt switching transitions. |
Applications
| High-Efficiency Server SMPS | 80+/85+ ATX Power Supplies |
|---|---|
|
Use Scenario: 90+/92+ compliant 1 kW+ server power supplies using LLC resonant topology with center-tapped transformer. IC Role / Device Role / Timing Role: Secondary-side synchronous rectifier controller managing dual N-MOSFETs; precisely times turn-on at body-diode conduction onset and turn-off at zero-current crossing. Use Value: Enables >94% full-load efficiency and maintains >90% efficiency at 10% load via sleep-mode activation - meeting stringent Energy Star and 80 PLUS Titanium requirements. |
Use Scenario: Compact all-in-one PC power supplies requiring high power density and low acoustic noise. IC Role / Device Role / Timing Role: Dual-channel SR driver coordinating gate timing with LLC resonant tank waveform phase - eliminating body-diode conduction losses in both half-cycles. Use Value: Reduces secondary-side conduction losses by >40% vs. Schottky diodes, lowering thermal stress and enabling smaller heatsinks and fanless operation. |
| Industrial AC-DC Adapters | High-Power USB-C PD Chargers |
|
Use Scenario: 300–600 W industrial SMPS operating across wide ambient temperatures (–40°C to +105°C). IC Role / Device Role / Timing Role: Robust SR controller with –40°C to +150°C junction rating and 150 °C/W RthJA - sustains accurate timing under thermal stress. Use Value: Maintains <1 mV threshold matching across temperature, ensuring consistent current sharing and reliability in unventilated enclosures. |
Use Scenario: Multi-port 100 W+ USB-C PD chargers using GaN-based LLC primary and synchronous rectification on secondary. IC Role / Device Role / Timing Role: Fast-propagation (60 ns max turn-off delay) SR driver minimizing reverse-recovery losses during high-frequency transient load steps. Use Value: Supports dynamic load response down to 10 µs while preserving ZCS turn-off - critical for maintaining PD compliance under rapid 0–100% load jumps. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous rectifier controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ON Semiconductor NCP4306DR2G | Single-channel SR controller with external MOSFET biasing; no integrated interlock or matched thresholds. | Requires dual ICs and external logic for two-MOSFET center-tap operation - increases BOM count and layout complexity. | Choose only when discrete channel control or cost-sensitive low-power (<150 W) designs outweigh integration benefits. |
| Vishay SiHP20N60E | 600 V N-channel MOSFET (not a controller); lacks gate driving, sensing, or timing logic. | Replaces SR switch only - cannot substitute SRK2000ATR's control functionality; requires companion controller. | Select only as a power device upgrade alongside existing SRK2000ATR design - not a functional alternative. |
Compared with NCP4306DR2G, SRK2000ATR integrates dual-channel interlocked control and threshold matching in one SO-8 package, reducing component count and timing skew; versus SiHP20N60E, it is a complete control solution - not a replacement power switch - enabling direct drop-in system-level optimization.
Availability
SRK2000ATR is available at Aetrix Electronics and suitable for high-efficiency server SMPS, 80+/85+ ATX power supplies, and industrial AC-DC adapters requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SRK2000ATR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, MCU, power, and automotive ICs with emphasis on energy efficiency and system integration.
SRK2000ATR belongs to ST's SR controller product line, engineered specifically for high-frequency LLC resonant converter secondary-side optimization - targeting ultra-high-efficiency AC-DC power conversion in datacenter, computing, and industrial applications.
FAQ
What is the purpose of the EN pin on the SRK2000ATR?
The EN pin serves three concurrent functions: it sets the drain-sense turn-off threshold (–12 mV or –25 mV), programs the VCC UVLO hysteresis (4.25 V turn-off, 4.5 V turn-on), and acts as an enable/disable input. Pulling EN to ground disables GD1/GD2 outputs, while biasing it via resistor divider allows remote on/off control and precise UVLO setting - all without external logic.
How does the SRK2000ATR prevent simultaneous conduction of the two SR MOSFETs?
The SRK2000ATR uses hardware interlocking logic between GD1 and GD2 state machines: when one gate driver is active, the other is forced into high-impedance state regardless of sensed drain voltage. This hardwired prevention - verified in internal block diagram and application schematic - eliminates shoot-through risk without relying on PCB layout or external timing components.
Can the SRK2000ATR be used with standard (non-logic-level) N-channel MOSFETs?
Yes - the SRK2000ATR's gate drivers deliver up to 12 V clamped output (typ. 11.9 V at 5 mA), sufficient to fully enhance standard 4.5 V-threshold N-MOSFETs. Its 3.5 A sink current ensures fast turn-off even with high gate charge devices, and the internal clamp protects against overvoltage when VCC exceeds 20 V - confirmed in Table 5 electrical characteristics.
What design considerations apply to the DVS1 and DVS2 pins?
DVS1/DVS2 require series resistors (e.g., 2 kΩ) to limit injected current during off-state drain voltage spikes (>36 V), per absolute maximum ratings. Layout must minimize trace inductance and avoid routing near noisy nodes; each pin connects directly to its MOSFET drain through shortest possible path to preserve nanosecond-scale timing integrity for zero-current detection.
SRK2000ATR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Applications:
- General Purpose
- Voltage - Input:
- -
- Voltage - Supply:
- 4.5V ~ 32V
- Current - Supply:
- 35 mA
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
SRK2000ATR FAQ
1.How can I place an order for SRK2000ATR through Aetrix?
Please submit a Request for Quotation (RFQ) for SRK2000ATR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SRK2000ATR reliable?
The price and inventory of SRK2000ATR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SRK2000ATR is usually 5 days.
3.What payment methods are accepted for SRK2000ATR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SRK2000ATR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SRK2000ATR?
SRK2000ATR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SRK2000ATR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SRK2000ATR?
For technical support, including SRK2000ATR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SRK2000ATR requirements.
6.How does Aetrix verify that SRK2000ATR is sourced from the original manufacturer or authorized distributors?
All SRK2000ATR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SRK2000ATR meets industry standards.
7.What is the process for return or replacement of SRK2000ATR?
All SRK2000ATR units undergo pre-shipment inspection (PSI). If there is an issue with SRK2000ATR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SRK2000ATR part is unused and in its original packaging.
Return procedure for SRK2000ATR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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