Microchip Technology SST26VF016BAT-104I/SM
- Part No.:
- SST26VF016BAT-104I/SM
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
SST26VF016BAT-104I/SM.pdf
- Description:
- IC FLASH 16MBIT SPI/QUAD 8SOIJ
- Quantity:
- Payment:

- Shipping:

Inventory:4,166
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SST26VF016BAT-104I/SM from Microchip Technology is a 16 Mbit Serial Quad I/O (SQI) flash memory IC operating at 2.3–3.6 V, supporting 104 MHz SPI and 80 MHz SQI interfaces, with uniform 4 KByte sectors, 100,000 write cycles endurance, and industrial temperature range (–40°C to +85°C), deployed in embedded boot code storage and firmware update applications.
For engineers reviewing the SST26VF016BAT-104I/SM datasheet, SST26VF016BAT-104I/SM pinout, SST26VF016BAT-104I/SM application, or SST26VF016BAT-104I/SM equivalent, key selection considerations include quad-I/O burst read performance, flexible block protection granularity (8/32/64 KByte overlay blocks), hardware write-protection via WP# pin, Security ID OTP capability, and WDFN-8 package compatibility with space-constrained PCB layouts.
Technical Context
The SST26VF016BAT-104I/SM implements a six-wire SQI interface (SCK, CE#, WP#, HOLD#, VDD, VSS, plus SIO[3:0] multiplexed I/O) enabling 4-bit data transfers at up to 80 MHz, while retaining full command-set compatibility with legacy SPI (Mode 0/3, x1/x2/x4). Its SuperFlash® split-gate cell architecture delivers faster erase (18 ms sector, 35 ms chip) and lower active current (15 mA @ 104 MHz) versus conventional NOR flash.
It integrates dual protection layers: volatile Block-Protection Register (BPR) with per-block write/read lock control and non-volatile Write-Lock Lock-Down Register (nVWLDR) for permanent OTP-based block lockdown; plus hardware-level WP# and HOLD# pins functional only in SPI mode (IOC = 0), disabled in SQI mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 16 Mbit (2 MByte) organized as thirty 64 KByte blocks, two 32 KByte blocks, eight 8 KByte parameter blocks, and uniform 4 KByte sectors - enables granular firmware partitioning and secure boot loader isolation. |
| Interface Speed | 104 MHz max SPI clock (2.7–3.6 V); 80 MHz max SQI clock (2.3–3.6 V) - supports high-throughput firmware loading without increasing pin count or board area. |
| Endurance & Retention | 100,000 program/erase cycles minimum; >100 years data retention - suitable for field-upgradable systems requiring long-term reliability without wear leveling. |
| Power Consumption | 15 mA typical active read current @ 104 MHz; 15 µA typical standby - reduces system-level power budget in always-on or low-duty-cycle IoT edge nodes. |
| Erase Performance | Sector/Block erase: 18 ms typ / 25 ms max; Chip erase: 35 ms typ / 50 ms max - accelerates factory programming and over-the-air (OTA) image validation cycles. |
| Security Features | 2 KByte Security ID with 64-bit factory-unique OTP identifier and user-programmable area; LSID/PSID commands enable irreversible lockout - meets secure boot root-of-trust requirements for certified embedded devices. |
| Operating Temperature | Industrial grade: –40°C to +85°C - validated for deployment in automotive infotainment head units, industrial PLCs, and outdoor networking equipment. |
Pinout & Package
Package: 8-contact WDFN (6 mm × 5 mm), RoHS-compliant, moisture-sensitive level 3 (MSL3).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CE# | Chip Enable | Active-low device select; must remain low throughout command sequence - enables multi-device daisy-chaining on shared SPI bus. |
| SIO[3:0] | Serial I/O (Quad) | Multiplexed bidirectional data lines for command/address/data in SQI mode; default SI/SO in SPI mode - eliminates separate input/output pins, reducing PCB routing complexity. |
| SCK | Serial Clock | Rising-edge latched input for commands/addresses; falling-edge shifted output for data - defines timing boundary for all serial transactions. |
| WP# | Write Protect | Hardware pin disabling writes to Block-Protection and Configuration registers when IOC=0 and WPEN=1 - provides tamper-resistant configuration lockdown independent of firmware state. |
| HOLD# | Hold Control | Pauses ongoing SPI reads without resetting internal state; inactive in SQI mode - allows host CPU to service higher-priority interrupts mid-transfer. |
| VDD | Power Supply | 2.3–3.6 V single supply - simplifies power design by eliminating auxiliary voltage rails required by older 5 V or 2.5 V flash parts. |
| VSS | Ground | Reference return path for all I/O and core logic - requires low-impedance connection to minimize noise coupling during high-speed bursts. |
Key Features
| Feature | Design Value |
|---|---|
| Serial Quad I/O (SQI) Interface | Four multiplexed I/O lines (SIO[3:0]) deliver 4× throughput vs. standard SPI at same clock frequency - cuts firmware load time by up to 75% without changing clock generator or layout. |
| Flexible Erase Architecture | Uniform 4 KByte sectors plus configurable 8/32/64 KByte overlay blocks - supports differential OTA updates where only changed partitions are rewritten, minimizing flash wear. |
| Write-Suspend Capability | WRSU/WRRE commands pause ongoing erase or program to service urgent reads - prevents real-time system stalls during background flash maintenance. |
| Two-Tier Protection Scheme | Volatile BPR + non-volatile nVWLDR with OTP lock-down bits - enables field-deployable security policies that survive power loss and resist runtime reconfiguration attacks. |
| Security ID with Factory OTP | 64-bit unique identifier pre-programmed at wafer test; 2 KByte user area programmable via PSID - provides cryptographic binding between hardware identity and firmware signature verification keys. |
Applications
| Boot Code Storage | Firmware Over-the-Air (OTA) Updates |
|---|---|
Use Scenario: Storing primary bootloader and initial firmware image in microcontroller-based edge gateways requiring cold-start reliability. IC Role / Device Role / Timing Role: Non-volatile storage for XIP-capable boot ROM accessed via SPI during reset vector fetch and early initialization. Use Value: 104 MHz SPI read speed and uniform 4 KByte sectors allow fast, deterministic boot sequence execution with minimal latency penalty. | Use Scenario: Hosting delta firmware patches and full-image binaries in smart metering endpoints with constrained bandwidth and battery life. IC Role / Device Role / Timing Role: Dual-bank update storage enabling atomic swap between active and staged firmware images without runtime corruption risk. Use Value: Write-suspend and fast sector erase (18 ms) permit background patch application while maintaining real-time metering accuracy. |
| Secure Boot Root-of-Trust | Industrial HMI Configuration Storage |
Use Scenario: Providing immutable hardware identity and signed firmware hash storage in medical diagnostic controllers subject to IEC 62304 compliance. IC Role / Device Role / Timing Role: Secure credential vault holding factory-programmed 64-bit ID and cryptographically verified boot manifest. Use Value: LSID-locked Security ID prevents runtime tampering; nVWLDR ensures protection bits survive power cycling and firmware resets. | Use Scenario: Retaining calibrated display parameters, language packs, and user preferences across power cycles in factory-floor HMIs. IC Role / Device Role / Timing Role: Parameter EEPROM replacement with higher density, faster write, and superior data retention (>100 years). Use Value: Eight 8 KByte parameter blocks support independent read/write locking - isolates critical calibration data from UI customization updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q16JVSIQ | 16 Mbit SPI-only (no SQI), 133 MHz max, 4 KByte sectors, no Security ID OTP, different status register bit mapping. | Lacks quad-I/O acceleration and hardware-secured identity - suitable only where SQI bandwidth and cryptographic binding are unnecessary. | Select if cost sensitivity outweighs performance/security needs and existing SPI controller lacks SQI support. |
| Cypress S25FL116K0XMFI011 | 16 Mbit SPI-only, 104 MHz, 4 KByte sectors, no OTP Security ID, supports QPI but not SQI protocol, different pinout (SOIC-8). | Missing SQI interface and factory-programmed ID - limits use in secure boot or high-throughput OTA contexts requiring native quad-burst efficiency. | Choose when migrating from legacy Spansion designs and board layout already accommodates SOIC-8 footprint. |
Compared with W25Q16JVSIQ and S25FL116K0XMFI011, the SST26VF016BAT-104I/SM delivers measurable advantages in boot latency (via SQI burst), field-upgrade resilience (via write-suspend), and hardware-rooted security (via OTP Security ID), making it optimal for next-generation certified embedded systems where performance, safety, and trust are co-prioritized.
Availability
SST26VF016BAT-104I/SM is available at Aetrix Electronics and suitable for industrial automation controllers, automotive infotainment modules, and medical edge devices requiring stable component supply, long-lifecycle support, and guaranteed RoHS-compliant sourcing.
Supply support for SST26VF016BAT-104I/SM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with global manufacturing and quality certifications including ISO 9001 and IATF 16949.
The SST26VF016BAT-104I/SM belongs to Microchip's Serial Quad I/O™ (SQI™) flash family, engineered specifically for high-reliability embedded systems needing faster boot times, robust firmware update mechanisms, and hardware-enforced security primitives.
FAQ
What is the maximum clock frequency supported by SST26VF016BAT-104I/SM in SQI mode?
The SST26VF016BAT-104I/SM supports up to 80 MHz in SQI mode when operated within the 2.3–3.6 V supply range. This is confirmed in the official Microchip datasheet DS20005262C, Section 1.0 Features. The 104 MHz rating applies only to standard SPI mode under 2.7–3.6 V conditions. SQI mode uses the same physical pins but quadruples effective throughput via 4-bit parallel data transfer per clock cycle.
Does SST26VF016BAT-104I/SM support hardware write protection using the WP# pin?
Yes, SST26VF016BAT-104I/SM supports hardware write protection via the WP# pin, but only when the IOC bit in the Configuration Register is set to '0' and the WPEN bit is set to '1'. In this configuration, pulling WP# low disables writes to the Block-Protection and Configuration registers. The WP# pin is disabled in SQI mode and functions exclusively in SPI single/dual-bit read modes, as specified in DS20005262C Section 4.2.
What package type is used for SST26VF016BAT-104I/SM, and what are its dimensions?
The SST26VF016BAT-104I/SM uses an 8-contact WDFN (WSON) package measuring 6 mm × 5 mm with exposed pad, per Microchip's official package drawing and DS20005262C Figure 2-2. This compact, lead-free RoHS-compliant package supports automated reflow assembly and offers improved thermal performance over SOIC-8 alternatives, making it ideal for space-constrained industrial and automotive PCBs.
Can SST26VF016BAT-104I/SM be used as a direct replacement for standard SPI flash devices?
Yes, SST26VF016BAT-104I/SM is fully command-set compatible with traditional SPI flash (e.g., 25-series), operating in SPI mode by default after power-on reset. It supports Mode 0/3, x1/x2/x4 protocols, and standard instructions like Read (03H), Page Program (02H), and Sector Erase (20H). No hardware changes are needed to migrate from legacy SPI flash, though enabling SQI requires issuing EQIO and setting IOC=1.
What is the purpose and capacity of the Security ID feature in SST26VF016BAT-104I/SM?
The Security ID in SST26VF016BAT-104I/SM is a dedicated 2 KByte area comprising a factory-programmed 64-bit unique identifier (immutable and unerasable) and a user-programmable segment. It supports PSID and LSID commands for writing and permanently locking the user portion. This feature enables hardware-rooted device authentication and secure boot chain binding, as documented in DS20005262C Section 4.3.
SST26VF016BAT-104I/SM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- SST26 SQI®
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 16Mbit
- Memory Organization:
- 2M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 1.5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIJ
SST26VF016BAT-104I/SM FAQ
1.How can I place an order for SST26VF016BAT-104I/SM through Aetrix?
Please submit a Request for Quotation (RFQ) for SST26VF016BAT-104I/SM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SST26VF016BAT-104I/SM reliable?
The price and inventory of SST26VF016BAT-104I/SM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SST26VF016BAT-104I/SM is usually 5 days.
3.What payment methods are accepted for SST26VF016BAT-104I/SM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SST26VF016BAT-104I/SM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SST26VF016BAT-104I/SM?
SST26VF016BAT-104I/SM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SST26VF016BAT-104I/SM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SST26VF016BAT-104I/SM?
For technical support, including SST26VF016BAT-104I/SM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SST26VF016BAT-104I/SM requirements.
6.How does Aetrix verify that SST26VF016BAT-104I/SM is sourced from the original manufacturer or authorized distributors?
All SST26VF016BAT-104I/SM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SST26VF016BAT-104I/SM meets industry standards.
7.What is the process for return or replacement of SST26VF016BAT-104I/SM?
All SST26VF016BAT-104I/SM units undergo pre-shipment inspection (PSI). If there is an issue with SST26VF016BAT-104I/SM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SST26VF016BAT-104I/SM part is unused and in its original packaging.
Return procedure for SST26VF016BAT-104I/SM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SST26VF016BAT-104I/SM Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

