Microchip Technology SST26VF032BT-104I/TD
- Part No.:
- SST26VF032BT-104I/TD
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
SST26VF032BT-104I/TD.pdf
- Description:
- IC FLASH 32MBIT SPI/QUAD 24TBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SST26VF032BT-104I/TD from Microchip Technology is a 32-Mbit Serial Quad I/O™ (SQI™) Flash memory IC designed for high-speed, low-pin-count embedded storage. It operates at up to 104 MHz (2.7–3.6 V), supports x1/x2/x4 SPI and full SQI protocols, features uniform 4-Kbyte sectors and 100,000 program/erase cycles, and is qualified for industrial temperature range (–40°C to +85°C) in an 8-contact WDFN package.
For engineers reviewing the SST26VF032BT-104I/TD datasheet, SST26VF032BT-104I/TD pinout, SST26VF032BT-104I/TD application, or SST26VF032BT-104I/TD equivalent, key selection considerations include its dual-mode interface (SPI default / configurable SQI), flexible block protection with OTP lock-down, 2-Kbyte Security ID with factory-unique 64-bit identifier, and support for write-suspend during active erase/program operations.
Technical Context
This device implements Microchip's proprietary SuperFlash® technology with split-gate cells and thick-oxide tunneling injectors, enabling faster erase (18 ms sector, 35 ms chip) and lower total energy per operation versus conventional Flash. Its six-wire SQI interface uses multiplexed SIO[3:0] for command/address/data transfer, quadrupling throughput over standard SPI at identical clock frequency.
The SST26VF032BT-104I/TD defaults to SPI mode at power-up (WP# and HOLD# enabled, SIO2/SIO3 disabled), but supports reconfiguration via IOC bit to enable quad I/O functionality. It includes dual protection layers: volatile Write Protection Lock-Down (LBPR) and nonvolatile nVWLDR for permanent block lock-down, plus hardware WP# pin control conditioned by WPEN and IOC bits.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 32 Mbit (4 MByte) organized as uniform 4-Kbyte sectors and mixed overlay blocks (8×8 KB, 2×32 KB, 62×64 KB) |
| Max Clock Frequency | 104 MHz at 2.7–3.6 V; enables high-throughput read/write without increasing pin count or board area |
| Erase Performance | Sector/Block erase: 18 ms typical; Chip erase: 35 ms typical - reduces firmware update latency |
| Endurance & Retention | 100,000 program/erase cycles minimum; >100 years data retention - suitable for long-life industrial logging |
| Supply Voltage Range | 2.3 V–3.6 V single supply - supports wide-input LDOs and battery-backed systems |
| Operating Temperature | –40°C to +85°C (Industrial grade) - validated for extended thermal cycling in embedded controllers |
| Security Features | One-time programmable 2-Kbyte Security ID with factory-unique 64-bit identifier and user-programmable area |
Pinout & Package
Package: 8-contact WDFN (6 mm × 5 mm), RoHS-compliant, moisture-sensitive level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CE# | Chip Enable | Active-low selection signal; must remain low throughout command sequence and data transfer |
| SIO0 (SI) | Serial Data Input (SPI) / Quad I/O 0 | Default input pin in SPI mode; becomes bidirectional SIO[0] in SQI mode after IOC=1 |
| SIO1 (SO) | Serial Data Output (SPI) / Quad I/O 1 | Default output pin in SPI mode; becomes bidirectional SIO[1] in SQI mode after IOC=1 |
| WP#/SIO2 | Write-Protect Input (SPI) / Quad I/O 2 | Hardware write-protection control in SPI mode; reconfigured as SIO[2] when IOC=1 |
| HOLD#/SIO3 | Hold Input (SPI) / Quad I/O 3 | Pauses serial communication without reset; reconfigured as SIO[3] when IOC=1 |
| VDD | Power Supply | 2.3–3.6 V main supply; powers internal logic and memory array |
| VSS | Ground | Reference ground for all I/O and core circuitry |
| SCK | Serial Clock | Timing reference; commands/addresses latched on rising edge; data shifted out on falling edge |
Key Features
| Feature | Design Value |
|---|---|
| Quad I/O Interface | Configurable via IOC bit to enable 4-bit multiplexed SIO[3:0], delivering up to 4× SPI bandwidth at same clock rate |
| Flexible Erase Architecture | Uniform 4-Kbyte sectors plus dedicated 8/32/64-Kbyte overlay blocks - enables granular firmware partitioning |
| Write-Suspend Capability | Allows suspension of ongoing erase/program to service urgent reads from other blocks - critical for real-time systems |
| Two-Tier Block Protection | Volatile LBPR lock-down and nonvolatile nVWLDR provide both field-reversible and permanent memory protection |
| Security ID with OTP Identifier | Factory-programmed unique 64-bit ID + 2-Kbyte user space - supports secure boot and device authentication |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Memory |
|---|---|
Use Scenario: Storing firmware images and configuration parameters in programmable logic controllers operating in harsh factory environments. IC Role / Device Role / Timing Role: Nonvolatile code storage with fast random-access read and reliable in-field updates via sector erase. Use Value: 100,000-cycle endurance and >100-year data retention ensure multi-decade deployment without refresh; 104 MHz read speed accelerates boot time. | Use Scenario: Holding boot code and safety-critical calibration data for camera/radar modules in automotive ADAS systems. IC Role / Device Role / Timing Role: AEC-Q100 Grade 2 qualified serial Flash providing secure, fast-access storage for ASIL-B compliant subsystems. Use Value: Factory-unique Security ID enables cryptographic binding to vehicle ECUs; write-suspend allows concurrent diagnostics during firmware update. |
| Medical IoT Sensor Node | Network Equipment Configuration |
Use Scenario: Logging sensor calibration data and usage history in portable diagnostic devices requiring long-term traceability. IC Role / Device Role / Timing Role: High-reliability data logger with OTP-protected identity and tamper-resistant parameter storage. Use Value: Nonvolatile nVWLDR permanently locks calibration blocks against accidental overwrite; 2.3 V min voltage supports coin-cell backup operation. | Use Scenario: Storing FPGA configuration bitstreams and switch/router firmware in telecom infrastructure equipment. IC Role / Device Role / Timing Role: High-speed serial Flash interfacing with FPGA or SoC via SQI bus to minimize PCB routing complexity. Use Value: 6 mm × 5 mm WDFN package saves board space vs. SOIC; continuous linear burst mode enables rapid bitstream loading. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial Flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q32JVSIQ | 32 Mbit SPI-only (no SQI); 133 MHz max; 100K cycles; same 8-lead SOIC/WSON packages | Lacks quad I/O and write-suspend; no Security ID or nVWLDR; simpler protection model | Select when SQI bandwidth is unnecessary and cost sensitivity outweighs advanced security features |
| Cypress S25FL132K0XMFI001 | 32 Mbit dual/quad SPI; 80 MHz max; 100K cycles; includes SFDP and 4-byte addressing support | No OTP Security ID; no write-suspend; different block protection granularity (64 KB only) | Select when SFDP-based auto-configuration is required and industrial temp range suffices |
Compared with W25Q32JVSIQ and S25FL132K0XMFI001, the SST26VF032BT-104I/TD uniquely combines SQI interface, write-suspend, OTP Security ID, and dual-tier block lock-down - making it optimal for secure, real-time embedded systems where interface flexibility and data integrity are prioritized over raw clock speed or legacy SPI compatibility.
Availability
SST26VF032BT-104I/TD is available at Aetrix Electronics and suitable for industrial automation, automotive ADAS, medical IoT, and network infrastructure applications requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.
Supply support for SST26VF032BT-104I/TD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and Flash memory solutions, serving industrial, automotive, and communications markets with high-reliability silicon and comprehensive development tools.
The SST26VF032BT-104I/TD belongs to Microchip's Serial Quad I/O™ (SQI™) Flash family, engineered to deliver high-speed, low-power, and secure nonvolatile storage for resource-constrained embedded systems demanding compact footprint and robust data integrity.
FAQ
What interface modes does the SST26VF032BT-104I/TD support?
The SST26VF032BT-104I/TD supports both traditional SPI (x1/x2/x4) and Serial Quad I/O™ (SQI) protocols. At power-up, it defaults to SPI mode with WP# and HOLD# enabled. The IOC bit in the Configuration register must be set to '1' to enable SQI mode and reconfigure SIO2/SIO3 pins. This dual-mode capability ensures backward compatibility while enabling higher bandwidth when needed.
How does the SST26VF032BT-104I/TD implement write protection?
The SST26VF032BT-104I/TD provides three layered write protection: (1) hardware via WP# pin (when WPEN=1 and IOC=0), (2) volatile lock-down via LBPR command, and (3) nonvolatile permanent lock-down via nVWLDR. Each 8-Kbyte parameter block and overlay block can be individually protected, and once nVWLDR bits are set, corresponding protection cannot be reversed - ensuring immutable firmware partitions.
What is the purpose of the Security ID feature in the SST26VF032BT-104I/TD?
The SST26VF032BT-104I/TD includes a 2-Kbyte Security ID with a factory-programmed unique 64-bit identifier and user-programmable area. This enables device authentication, secure boot binding, and anti-cloning measures. The LSID command permanently locks the entire Security ID space, preventing further writes - a critical requirement for certified medical or automotive systems using the SST26VF032BT-104I/TD.
Can the SST26VF032BT-104I/TD suspend an ongoing erase or program operation?
Yes, the SST26VF032BT-104I/TD supports write-suspend via the WRSU instruction. This allows interruption of active sector/block erase or page program to perform urgent reads from other memory regions. After suspension, the WSP or WSE bit in the STATUS register indicates the suspended state, and WRRE resumes the operation - essential for deterministic response in real-time embedded applications using the SST26VF032BT-104I/TD.
What package and temperature grade is specified for the SST26VF032BT-104I/TD?
The SST26VF032BT-104I/TD is packaged in an 8-contact WDFN (6 mm × 5 mm) and rated for the Industrial temperature range (–40°C to +85°C). The "I" suffix in the part number explicitly denotes this industrial grade, and the "T" indicates tape-and-reel packaging. It is RoHS-compliant and moisture-sensitive level 3, requiring appropriate handling per J-STD-020.
SST26VF032BT-104I/TD Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- SST26 SQI®
- Package/Case:
- 24-TBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 32Mbit
- Memory Organization:
- 4M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 1.5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TBGA (6x8)
SST26VF032BT-104I/TD FAQ
1.How can I place an order for SST26VF032BT-104I/TD through Aetrix?
Please submit a Request for Quotation (RFQ) for SST26VF032BT-104I/TD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SST26VF032BT-104I/TD reliable?
The price and inventory of SST26VF032BT-104I/TD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SST26VF032BT-104I/TD is usually 5 days.
3.What payment methods are accepted for SST26VF032BT-104I/TD?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SST26VF032BT-104I/TD transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SST26VF032BT-104I/TD?
SST26VF032BT-104I/TD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SST26VF032BT-104I/TD order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SST26VF032BT-104I/TD?
For technical support, including SST26VF032BT-104I/TD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SST26VF032BT-104I/TD requirements.
6.How does Aetrix verify that SST26VF032BT-104I/TD is sourced from the original manufacturer or authorized distributors?
All SST26VF032BT-104I/TD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SST26VF032BT-104I/TD meets industry standards.
7.What is the process for return or replacement of SST26VF032BT-104I/TD?
All SST26VF032BT-104I/TD units undergo pre-shipment inspection (PSI). If there is an issue with SST26VF032BT-104I/TD, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SST26VF032BT-104I/TD part is unused and in its original packaging.
Return procedure for SST26VF032BT-104I/TD:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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