Microchip Technology SST26VF032BT-80E/SM70SVAO
- Part No.:
- SST26VF032BT-80E/SM70SVAO
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
SST26VF032BT-80E/SM70SVAO.pdf
- Description:
- IC FLASH 32MBIT SPI/QUAD 8SOIJ
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SST26VF032BT-80E/SM70SVAO from Microchip Technology is a 32-Mbit Serial Quad I/O™ (SQI™) Flash memory IC designed for high-speed, low-pin-count embedded storage in space-constrained applications. It operates at 2.3V–3.6V, supports 80 MHz max clock frequency, delivers 100,000 program/erase cycles, and features uniform 4-Kbyte sectors with flexible block protection - deployed in industrial control firmware storage and boot code retention.
For engineers reviewing the SST26VF032BT-80E/SM70SVAO datasheet, SST26VF032BT-80E/SM70SVAO pinout, SST26VF032BT-80E/SM70SVAO application, or SST26VF032BT-80E/SM70SVAO equivalent, key selection criteria include SQI vs. SPI mode configuration (IOC bit), hardware write-protection behavior (WP#/WPEN interaction), burst-read timing compliance, and parameter-block lock-down capability for secure boot partitioning.
Technical Context
This device implements a six-wire, 4-bit multiplexed I/O interface (SIO[3:0]) supporting both legacy SPI (Mode 0/3, x1/x2) and high-throughput SQI protocols. Its SuperFlash® split-gate cell architecture enables faster erase (18 ms sector, 35 ms chip) and lower active current (15 mA @ 80 MHz) versus conventional NOR Flash.
Power-on default is SPI mode with WP# and HOLD# enabled (IOC = 0); SQI operation requires explicit EQIO command and IOC bit set to '1'. The STATUS register provides real-time BUSY/WEL/WPLD monitoring, while the Configuration register controls I/O mapping, WPEN, and BPNV state - all nonvolatile except WPLD (volatile lock-down).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 32 Mbit (4 MByte) organized as 62 × 64-Kbyte + 2 × 32-Kbyte + 8 × 8-Kbyte + uniform 4-Kbyte sectors |
| Interface Protocol | Configurable SPI (x1/x2) or SQI (x4) via IOC bit; supports Mode 0/3 clock polarity/phasing |
| Max Clock Frequency | 80 MHz at 2.3V–3.6V - defines maximum sustained read throughput of ~320 MB/s in SQI mode |
| Erase Performance | Sector (4 Kbyte): 18 ms typ; Chip Erase: 35 ms typ - enables fast field firmware updates |
| Data Retention | >100 years - validated for long-life industrial deployments without refresh |
| Endurance | 100,000 program/erase cycles per sector - sufficient for bootloader and configuration storage |
| Security ID | 2-Kbyte OTP area: factory-programmed 64-bit unique ID + user-programmable segment, lockable via LSID |
| Operating Temp | Industrial Plus: –40°C to +105°C - qualified for extended-temperature edge computing and automotive infotainment |
Pinout & Package
Package: 8-contact WDFN (6 mm × 5 mm), RoHS-compliant, moisture-sensitive level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CE# | Chip Enable | Active-low enable for all serial commands; must remain low during full instruction sequence |
| SIO0/SI | Serial Data I/O / Input | Default SPI input (SI) or bidirectional quad I/O (SIO0); latched on SCK rising edge |
| SIO1/SO | Serial Data I/O / Output | Default SPI output (SO) or bidirectional quad I/O (SIO1); driven on SCK falling edge |
| WP#/SIO2 | Write-Protect Input / I/O | Hardware write-lock for protection registers when IOC=0 & WPEN=1; reconfigured as SIO2 in SQI mode |
| HOLD#/SIO3 | Communication Hold / I/O | Pauses ongoing SPI reads without resetting state; disabled in SQI mode; reconfigured as SIO3 when IOC=1 |
| SCK | Serial Clock | Timing reference for all transfers; rising edge samples inputs, falling edge outputs data |
| VDD | Power Supply | 2.3V–3.6V single supply; powers core logic and I/O buffers |
| VSS | Ground | Reference return path for all signals and internal circuitry |
Key Features
| Feature | Design Value |
|---|---|
| Quad I/O Burst Read | Enables continuous linear or wrap-around bursts (8/16/32/64-byte) at up to 320 MB/s effective bandwidth |
| Flexible Block Protection | Independent lock-down of 64-Kbyte, 32-Kbyte, and 8-Kbyte blocks - including read-lock for top/bottom parameter sectors |
| Write-Suspend Capability | Allows interruption of active Program/Erase to service urgent reads from other sectors - critical for real-time systems |
| Nonvolatile Write Lock-Down | One-time programmable nVWLDR bits permanently fix block protection status - prevents runtime tampering with boot partitions |
| Security ID with Lockout | Factory-unique 64-bit ID + 2-Kbyte user space, secured by LSID command - supports device authentication and license binding |
| Low-Power Standby | 15 µA typical current draw in standby - suitable for battery-backed or energy-harvesting applications |
Applications
| Industrial PLC Firmware Storage | Automotive Infotainment Boot Memory |
|---|---|
Use Scenario: Storing and executing firmware images for programmable logic controllers operating in harsh factory environments. IC Role / Device Role / Timing Role: Nonvolatile boot code and parameter storage with AEC-Q100 Grade 2 qualification and –40°C to +105°C operation. Use Value: Uniform 4-Kbyte sectors enable atomic firmware updates; 100,000-cycle endurance ensures >10-year field life under frequent OTA updates. | Use Scenario: Hosting boot loader and safety-critical initialization code for head-unit microcontrollers in vehicles. IC Role / Device Role / Timing Role: Secure, high-reliability flash memory with factory-programmed Security ID and permanent block lock-down for boot partition integrity. Use Value: nVWLDR prevents runtime modification of boot sector; 100+ year data retention guarantees firmware persistence over vehicle lifetime. |
| Medical Diagnostic Equipment Configuration | Edge AI Gateway Firmware Cache |
Use Scenario: Retaining calibration data, user preferences, and regulatory-compliant configuration profiles in portable ultrasound and imaging devices. IC Role / Device Role / Timing Role: Parameter-block protected storage with read-lock capability on top/bottom 8-Kbyte sectors for HIPAA-compliant data isolation. Use Value: Read-lock returns 00H on unauthorized access - enforces data confidentiality without host-side encryption overhead. | Use Scenario: Caching inference models and firmware patches in low-power edge gateways deployed in remote IoT infrastructure. IC Role / Device Role / Timing Role: High-bandwidth SQI interface (80 MHz) paired with burst-read optimization for rapid model loading from external memory. Use Value: Continuous linear burst mode reduces read latency by >40% vs. standard SPI, accelerating AI pipeline startup time. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q32JW | 32 Mbit, 1.8V/3.3V dual supply; supports octal DTR mode; no built-in Security ID or nVWLDR | Lacks factory-unique ID and permanent block lock-down - unsuitable for secure boot or regulatory traceability | Select when ultra-low voltage (1.8V) operation or octal interface is required; verify absence of hardware security features aligns with system threat model |
| Cypress S25FL132K | 32 Mbit, 2.7V–3.6V; supports XIP with prefetch buffer; no SQI mode; different command set and protection granularity | No quad I/O protocol support; uses 64-Kbyte uniform sectors only - no 8-Kbyte parameter blocks or overlay flexibility | Choose for execute-in-place (XIP) applications requiring deterministic latency; avoid if SQI bandwidth or fine-grained protection is mandatory |
Compared with Winbond W25Q32JW and Cypress S25FL132K, SST26VF032BT-80E/SM70SVAO uniquely combines SQI throughput, factory-secured 64-bit ID, and one-time programmable block lock-down - making it the only option among the three qualified for AEC-Q100 Grade 2 and certified for secure boot partitioning in regulated systems.
Availability
SST26VF032BT-80E/SM70SVAO is available at Aetrix Electronics and suitable for industrial PLC firmware storage, automotive infotainment boot memory, and medical diagnostic equipment configuration requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for SST26VF032BT-80E/SM70SVAO includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontroller, mixed-signal, analog, and Flash memory solutions, headquartered in Chandler, Arizona, with global design, manufacturing, and sales operations.
The SST26VF032B series belongs to Microchip's Serial Quad I/O™ Flash family, engineered specifically for high-reliability embedded systems demanding fast, secure, and low-pin-count nonvolatile storage - especially where firmware integrity, long-term data retention, and AEC-Q100 compliance are critical.
FAQ
What is the default I/O configuration mode for SST26VF032BT-80E/SM70SVAO at power-up?
The SST26VF032BT-80E/SM70SVAO powers up in SPI mode with IOC = 0, enabling WP# and HOLD# pins and disabling SIO2/SIO3. To activate SQI mode, the host must issue the EQIO command and set IOC = 1 in the Configuration register. This default ensures backward compatibility with legacy SPI controllers while allowing explicit upgrade to higher bandwidth.
Does SST26VF032BT-80E/SM70SVAO support both Mode 0 and Mode 3 SPI clocking?
Yes, SST26VF032BT-80E/SM70SVAO supports both SPI Mode 0 (CPOL = 0, CPHA = 0) and Mode 3 (CPOL = 1, CPHA = 1). In both modes, data is sampled on the rising edge of SCK and driven on the falling edge. The device automatically adapts to the master's clock idle state - low for Mode 0, high for Mode 3 - without requiring configuration changes.
How does hardware write protection work on SST26VF032BT-80E/SM70SVAO?
Hardware write protection on SST26VF032BT-80E/SM70SVAO requires both WPEN = 1 (nonvolatile) and WP# = low, but only functions in SPI mode (IOC = 0). It protects only the Block Protection and Configuration registers - not the main memory array. If WP# is grounded but WPEN = 0 (factory default), protection is inactive. The volatile WPLD bit can further lock down protection settings after power cycle.
Can SST26VF032BT-80E/SM70SVAO perform simultaneous read and write operations?
No, SST26VF032BT-80E/SM70SVAO does not support true concurrent read/write. However, it supports Write-Suspend (WRSU command), allowing an active Program or Erase operation to be paused so another sector/block can be read. This enables time-critical reads without aborting or waiting for full erase/program completion - essential for real-time interrupt handling.
What is the purpose of the Security ID feature in SST26VF032BT-80E/SM70SVAO?
The Security ID in SST26VF032BT-80E/SM70SVAO provides a 2-Kbyte OTP area containing a factory-programmed 64-bit unique identifier and a user-programmable segment. It supports device authentication, license binding, and secure boot verification. Once locked via LSID command, the entire Security ID space becomes permanently read-only - preventing tampering with identity-critical data.
SST26VF032BT-80E/SM70SVAO Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- SST26 SQI®
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 32Mbit
- Memory Organization:
- 4M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 80 MHz
- Write Cycle Time - Word, Page:
- 1.5ms
- Access Time:
- -
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIJ
SST26VF032BT-80E/SM70SVAO FAQ
1.How can I place an order for SST26VF032BT-80E/SM70SVAO through Aetrix?
Please submit a Request for Quotation (RFQ) for SST26VF032BT-80E/SM70SVAO on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SST26VF032BT-80E/SM70SVAO reliable?
The price and inventory of SST26VF032BT-80E/SM70SVAO are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SST26VF032BT-80E/SM70SVAO is usually 5 days.
3.What payment methods are accepted for SST26VF032BT-80E/SM70SVAO?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SST26VF032BT-80E/SM70SVAO transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SST26VF032BT-80E/SM70SVAO?
SST26VF032BT-80E/SM70SVAO orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SST26VF032BT-80E/SM70SVAO order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SST26VF032BT-80E/SM70SVAO?
For technical support, including SST26VF032BT-80E/SM70SVAO datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SST26VF032BT-80E/SM70SVAO requirements.
6.How does Aetrix verify that SST26VF032BT-80E/SM70SVAO is sourced from the original manufacturer or authorized distributors?
All SST26VF032BT-80E/SM70SVAO products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SST26VF032BT-80E/SM70SVAO meets industry standards.
7.What is the process for return or replacement of SST26VF032BT-80E/SM70SVAO?
All SST26VF032BT-80E/SM70SVAO units undergo pre-shipment inspection (PSI). If there is an issue with SST26VF032BT-80E/SM70SVAO, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SST26VF032BT-80E/SM70SVAO part is unused and in its original packaging.
Return procedure for SST26VF032BT-80E/SM70SVAO:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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