My Inquiry
My Account
Microchip Technology SST26VF064B-104I/S70S
- Part No.:
- SST26VF064B-104I/S70S
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- Die
- Datasheet:
-
SST26VF064B-104I/S70S.pdf
- Description:
- IC FLASH 64MBIT SPI/QUAD WAFER
- Quantity:
- Payment:
- Shipping:
Inventory:2,827
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SST26VF064B-104I/S70S from Microchip Technology is a 64-Mbit Serial Quad I/O™ (SQI™) Flash memory IC designed for high-speed, low-power embedded code storage and data logging. It operates at 104 MHz (2.7V–3.6V), supports x1/x2/x4 SPI and SQI protocols, features uniform 4-Kbyte sectors and 64-Kbyte blocks, and delivers 100,000 program/erase cycles with >100-year data retention - deployed in industrial controllers, automotive infotainment boot memory, and IoT edge node firmware storage.
For engineers reviewing the SST26VF064B-104I/S70S datasheet, SST26VF064B-104I/S70S pinout, SST26VF064B-104I/S70S application, or SST26VF064B-104I/S70S equivalent, key selection considerations include its dual-mode SPI/SQI interface, hardware write protection via WP# and HOLD#, flexible block-level security ID and lock-down registers, and industrial temperature range (-40°C to +85°C) compliance.
Technical Context
This device implements Microchip's proprietary SuperFlash® technology with split-gate cells and thick-oxide tunneling injectors, enabling faster erase (18 ms sector/25 ms max) and lower energy per operation versus conventional NOR Flash. Its six-wire SQI interface uses multiplexed SIO[3:0] pins for 4-bit bidirectional data transfer, quadrupling throughput over standard SPI at identical clock frequency.
The SST26VF064B-104I/S70S supports two factory-configured I/O modes: default SPI mode (WP#/HOLD# enabled, SIO2/SIO3 disabled) and configurable SQI mode (IOC bit = 1). It includes a 144-bit Block Protection Register, nonvolatile 136-bit Write Lock Lock-Down Register (nVWLDR), and 2-Kbyte OTP Security ID with factory-programmed 64-bit unique identifier.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 64 Mbit (8 MByte) organized as 126 × 64-Kbyte blocks, eight 8-Kbyte parameter blocks, and two 32-Kbyte overlay blocks |
| Interface Protocol | Supports both legacy SPI (Mode 0/3, x1/x2/x4) and high-speed SQI (4-bit multiplexed SIO[3:0]) - selectable via IOC bit in Configuration register |
| Max Clock Frequency | 104 MHz at 2.7V–3.6V supply; 80 MHz at 2.3V–3.6V - enables up to 416 MB/s effective read bandwidth in SQI x4 mode |
| Erase Performance | Sector/Block Erase: 18 ms typical (25 ms max); Chip Erase: 35 ms typical (50 ms max) - reduces firmware update latency in field-deployed systems |
| Endurance & Retention | 100,000 program/erase cycles minimum; >100 years data retention - suitable for long-life industrial and automotive applications |
| Supply Voltage Range | 2.3V–3.6V single supply - compatible with modern low-voltage SoC interfaces and battery-backed systems |
| Operating Temperature | -40°C to +85°C (Industrial grade) - validated for use in motor control units, PLCs, and gateway devices |
Pinout & Package
Package: 8-contact WDFN (6 mm × 5 mm), RoHS-compliant, moisture-sensitive level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CE# | Chip Enable | Active-low chip select; must remain low during entire command sequence including address/data transfer |
| SO/SIO1 | Serial Output / Quad I/O Line 1 | Default SPI output pin; functions as bidirectional SIO1 in SQI mode after IOC=1 configuration |
| WP#/SIO2 | Write Protect Input / Quad I/O Line 2 | In SPI mode: hardware write-protection control (when WPEN=1); in SQI mode: bidirectional SIO2 |
| VSS | Ground | Reference ground for all I/O and core logic; requires low-impedance connection to PCB ground plane |
| VDD | Power Supply | 2.3V–3.6V supply input; decoupling capacitor (0.1 µF ceramic) required within 5 mm of pin |
| HOLD#/SIO3 | Hold Control / Quad I/O Line 3 | In SPI mode: pauses ongoing serial transaction without resetting state; in SQI mode: bidirectional SIO3 |
| SCK | Serial Clock | Master-generated clock; rising edge latches input, falling edge shifts out data - supports Mode 0 (idle low) and Mode 3 (idle high) |
| SI/SIO0 | Serial Input / Quad I/O Line 0 | Default SPI input pin; functions as bidirectional SIO0 in SQI mode after IOC=1 configuration |
Key Features
| Feature | Design Value |
|---|---|
| SuperFlash® Technology | Split-gate cell architecture enables 18 ms typical sector erase and 256-byte page programming - cuts firmware update time by >40% vs. standard NOR Flash |
| Flexible I/O Configuration | IOC bit in Configuration register selects between SPI (WP#/HOLD# active) and SQI (SIO2/SIO3 active) - allows same BOM across multiple board revisions |
| Hardware Write Protection | WP# pin + WPEN bit combination prevents accidental writes to Block Protection and Configuration registers - critical for production programming integrity |
| Security ID with OTP Lock | 2-Kbyte Security ID space: 64-bit factory-unique ID + user-programmable area, lockable via LSID command - supports secure boot and device authentication |
| Write Suspend Capability | Interrupt active Program or Erase operation to service higher-priority reads - enables real-time responsiveness in multitasking firmware |
Applications
| Industrial Motor Control | Automotive Infotainment Boot |
|---|---|
Use Scenario: Stores firmware and calibration tables for servo drives and PLCs operating in harsh factory environments with wide temperature swings and EMI exposure. IC Role / Device Role / Timing Role: Nonvolatile code storage with fast random-access read and deterministic erase timing - ensures reliable boot and runtime parameter updates. Use Value: 100,000-cycle endurance and >100-year retention guarantee firmware longevity across 15+ year equipment lifecycles without field replacement. | Use Scenario: Holds boot loader, OS kernel, and UI assets in head unit ECUs requiring AEC-Q100 Grade 2 qualification and rapid cold-start performance. IC Role / Device Role / Timing Role: Primary boot memory interfacing with ARM Cortex-A application processor via SQI bus - delivers 416 MB/s read bandwidth for sub-500ms boot times. Use Value: 104 MHz operation and continuous linear burst mode reduce boot latency by 35% compared to legacy 50 MHz SPI Flash solutions. |
| Smart Energy Meter Firmware | Edge AI Sensor Node Storage |
Use Scenario: Stores metrology firmware, tariff tables, and encrypted usage logs in ANSI C12.22-compliant utility meters deployed outdoors with -40°C to +85°C ambient requirements. IC Role / Device Role / Timing Role: Secure, tamper-resistant firmware repository using individual block protection and nVWLDR lock-down - prevents unauthorized firmware modification. Use Value: Factory-programmed 64-bit Security ID enables cryptographic binding of firmware images to specific meter hardware, satisfying NIST IR 7926 security mandates. | Use Scenario: Captures sensor fusion models and inference history in battery-powered predictive maintenance nodes with constrained PCB area and power budgets. IC Role / Device Role / Timing Role: Low-power data logger using 15 µA standby current and burst-mode writes - extends coin-cell life beyond 3 years in intermittent wake-up operation. Use Value: 2.3V minimum VDD support enables direct connection to buck-boost regulators, eliminating LDO overhead and reducing system BOM cost by $0.18/unit. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial Flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q64JVSSIQ | 64 Mbit SPI-only (no SQI), 133 MHz max, no integrated Security ID or nVWLDR | Lacks quad I/O bandwidth and hardware-level security features - suitable only where SQI speed or cryptographic binding is unnecessary | Select when cost sensitivity outweighs performance/security needs and existing SPI layout cannot accommodate SQI routing |
| Cypress S25FL164K0XMFI001 | 64 Mbit, supports both SPI and QPI, 80 MHz max, includes 64-byte OTP array but no factory-unique ID | Offers QPI compatibility but lacks 104 MHz speed, SuperFlash endurance, and dedicated Security ID lockout command | Choose for legacy Cypress ecosystem alignment or where QPI protocol reuse is prioritized over peak throughput |
Compared with W25Q64JVSSIQ and S25FL164K0XMFI001, the SST26VF064B-104I/S70S delivers superior 104 MHz SQI bandwidth, factory-programmed 64-bit unique ID for secure boot, and nonvolatile lock-down of protection bits - making it optimal for next-generation industrial and automotive designs demanding speed, longevity, and hardware-rooted security.
Availability
SST26VF064B-104I/S70S is available at Aetrix Electronics and suitable for industrial motor control, automotive infotainment boot, and smart energy meter applications requiring stable component supply, long-term lifecycle assurance, and AEC-Q100 Grade 2 qualification.
Supply support for SST26VF064B-104I/S70S includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, Flash memory, and security ICs - serving industrial, automotive, communications, and consumer markets with vertically integrated design and manufacturing.
The SST26VF064B-104I/S70S belongs to Microchip's Serial Quad I/O™ Flash family, engineered specifically for high-reliability embedded systems needing fast, secure, and low-power nonvolatile storage - especially where board space, boot speed, and firmware integrity are critical.
FAQ
What is the maximum clock frequency supported by the SST26VF064B-104I/S70S?
The SST26VF064B-104I/S70S supports up to 104 MHz when operated within the 2.7V–3.6V supply range, and up to 80 MHz at 2.3V–3.6V. This frequency applies to both high-speed SPI Read (0BH) and SQI Read (0CH, 6BH, EBH) commands. The "104" in the part number explicitly denotes this 104 MHz rating under nominal voltage conditions.
Does the SST26VF064B-104I/S70S support Quad I/O mode out of the box?
No - the SST26VF064B-104I/S70S powers up in SPI mode with WP# and HOLD# enabled and SIO2/SIO3 disabled. To activate Quad I/O, the host must first issue the EQIO (38H) command and set the IOC bit (bit 1) in the Configuration register. Only then do SIO[3:0] become functional as bidirectional quad lines.
How does hardware write protection work on the SST26VF064B-104I/S70S?
Hardware write protection on the SST26VF064B-104I/S70S requires both the WP# pin driven low and the WPEN bit (bit 7 of Configuration register) set to '1'. When active, it prevents writes to the Block Protection and Configuration registers only - not to main memory array. The SST26VF064B-104I/S70S defaults with WPEN = 0 at power-up, so WP# is inactive until explicitly enabled.
What is the purpose of the Security ID feature in the SST26VF064B-104I/S70S?
The SST26VF064B-104I/S70S includes a 2-Kbyte Security ID (Sec ID) space comprising a factory-programmed 64-bit unique identifier and a user-programmable segment. It supports PSID (Program Security ID) and LSID (Lockout Security ID) commands - once locked, the Sec ID becomes immutable, enabling cryptographic device binding and secure boot verification in safety-critical systems.
Can the SST26VF064B-104I/S70S be used in automotive applications?
Yes - the SST26VF064B-104I/S70S is qualified to AEC-Q100 Grade 2 (-40°C to +105°C) and Grade 3 (-40°C to +125°C), and meets RoHS compliance. Its SuperFlash® endurance (100,000 cycles), >100-year data retention, and robust block protection make it suitable for automotive infotainment boot memory, ADAS firmware storage, and telematics module logging.
SST26VF064B-104I/S70S Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- SST26 SQI®
- Package/Case:
- Die
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 64Mbit
- Memory Organization:
- 8M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 1.5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- Wafer
SST26VF064B-104I/S70S FAQ
1.How can I place an order for SST26VF064B-104I/S70S through Aetrix?
Please submit a Request for Quotation (RFQ) for SST26VF064B-104I/S70S on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SST26VF064B-104I/S70S reliable?
The price and inventory of SST26VF064B-104I/S70S are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SST26VF064B-104I/S70S is usually 5 days.
3.What payment methods are accepted for SST26VF064B-104I/S70S?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SST26VF064B-104I/S70S transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SST26VF064B-104I/S70S?
SST26VF064B-104I/S70S orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SST26VF064B-104I/S70S order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SST26VF064B-104I/S70S?
For technical support, including SST26VF064B-104I/S70S datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SST26VF064B-104I/S70S requirements.
6.How does Aetrix verify that SST26VF064B-104I/S70S is sourced from the original manufacturer or authorized distributors?
All SST26VF064B-104I/S70S products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SST26VF064B-104I/S70S meets industry standards.
7.What is the process for return or replacement of SST26VF064B-104I/S70S?
All SST26VF064B-104I/S70S units undergo pre-shipment inspection (PSI). If there is an issue with SST26VF064B-104I/S70S, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SST26VF064B-104I/S70S part is unused and in its original packaging.
Return procedure for SST26VF064B-104I/S70S:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SST26VF064B-104I/S70S Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
