Microchip Technology SST26VF064B-104I/WF70S
- Part No.:
- SST26VF064B-104I/WF70S
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- Die
- Datasheet:
-
SST26VF064B-104I/WF70S.pdf
- Description:
- IC FLASH 64MBIT SPI/QUAD WAFER
- Quantity:
- Payment:

- Shipping:

Inventory:4,361
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SST26VF064B-104I/WF70S from Microchip Technology is a 64-Mbit Serial Quad I/O™ (SQI™) Flash memory IC designed for high-speed, low-power embedded code storage and data logging. It operates at 104 MHz max clock frequency (2.7V–3.6V), supports x1/x2/x4 SPI and full SQI protocols, features uniform 4-Kbyte sectors and 100,000 write/erase cycles, and is qualified for industrial temperature range (–40°C to +85°C) in an 8-contact WDFN (6 mm × 8 mm) package.
For engineers reviewing the SST26VF064B-104I/WF70S datasheet, SST26VF064B-104I/WF70S pinout, SST26VF064B-104I/WF70S application, or SST26VF064B-104I/WF70S equivalent, key selection considerations include quad-I/O burst performance, hardware write protection via WP#/HOLD# pins, flexible block-level security lock-down, and compatibility with both legacy SPI and accelerated SQI host interfaces.
Technical Context
This device implements Microchip's proprietary SuperFlash® technology with split-gate cells and thick-oxide tunneling, enabling faster erase (18 ms sector/25 ms max) and lower total energy per operation versus conventional NOR Flash. Its dual-mode interface supports backward-compatible SPI (Mode 0/3) and high-throughput SQI using multiplexed SIO[3:0] pins.
The SST26VF064B-104I/WF70S defaults at power-up to SPI mode with WP# and HOLD# enabled (IOC = 0), distinguishing it from the SST26VF064BA variant. It integrates a 144-bit Block Protection Register, nonvolatile Write Lock Lock-Down register (136-bit), and 2-Kbyte Security ID with factory-programmed 64-bit unique identifier and user-programmable area.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 64 Mbit (8 MByte) organized as 126 × 64-Kbyte blocks + overlay blocks |
| Max Clock Frequency | 104 MHz at 2.7V–3.6V supply - enables 416 MB/s theoretical SQI read throughput |
| Erase Performance | 18 ms typical sector erase (4-Kbyte); 35 ms typical chip erase - reduces firmware update latency |
| Endurance & Retention | 100,000 program/erase cycles minimum; >100 years data retention - suitable for long-life industrial logging |
| Supply Voltage Range | 2.7V–3.6V (standard), or 2.3V–3.6V (low-voltage mode) - supports mixed-voltage system integration |
| Operating Temperature | –40°C to +85°C (Industrial grade) - validated for extended thermal cycling in control systems |
| Security Features | OTP 2-Kbyte Security ID with factory-unique 64-bit ID + user-programmable segment - enables secure boot authentication |
Pinout & Package
Package: 8-contact WDFN (6 mm × 8 mm), RoHS-compliant, moisture sensitivity level (MSL) 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CE# | Chip Enable | Active-low chip select; must remain low during command/data sequences to prevent premature termination |
| SO/SIO1 | Serial Output / Quad I/O 1 | Default SPI output pin; functions as bidirectional SIO1 in SQI mode after IOC=1 configuration |
| WP#/SIO2 | Write Protect Input / Quad I/O 2 | Hardware write-protection control for Block Protection register when IOC=0 and WPEN=1 |
| VSS | Ground | Reference return path for all digital and analog circuitry; requires low-impedance PCB connection |
| VDD | Power Supply | 2.7V–3.6V core supply; decoupling capacitor (0.1 µF) required adjacent to pin |
| HOLD#/SIO3 | Hold Control / Quad I/O 3 | Pauses ongoing SPI transfers without resetting state; disabled in SQI mode and when IOC=1 |
| SCK | Serial Clock | Timing reference for all serial operations; supports Mode 0 (SCK idle low) and Mode 3 (SCK idle high) |
| SI/SIO0 | Serial Input / Quad I/O 0 | Default SPI input pin; functions as bidirectional SIO0 in SQI mode after IOC=1 configuration |
Key Features
| Feature | Design Value |
|---|---|
| Quad I/O Interface | Enables 4-bit parallel data transfer on SIO[3:0], quadrupling effective bandwidth vs. standard SPI at same clock rate |
| Flexible Erase Architecture | Uniform 4-Kbyte sectors plus configurable 8/32/64-Kbyte overlay blocks - supports partial firmware updates without full chip erase |
| Write Suspend Capability | Allows interrupting active Program or Erase to service higher-priority reads - critical for real-time system responsiveness |
| Hardware + Software Protection | WP# pin + volatile/nonvolatile lock-down bits enable layered security: temporary (WPLD) and permanent (nVWLDR) block write lock |
| Security ID with OTP Segment | Factory-programmed 64-bit unique ID ensures traceability; user-programmable 2-Kbyte area supports cryptographic key storage |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Memory |
|---|---|
Use Scenario: Storing firmware images and configuration parameters in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Nonvolatile code storage with fast random access and deterministic erase timing for safe field updates. Use Value: 104 MHz SQI read speed and 18 ms sector erase reduce machine downtime during firmware upgrades; industrial temperature rating ensures reliability in uncontrolled cabinet environments. | Use Scenario: Holding boot code and sensor calibration data for vision-based driver assistance modules operating in automotive under-hood conditions. IC Role / Device Role / Timing Role: AEC-Q100 Grade 2 qualified boot memory providing secure, tamper-resistant storage for safety-critical initialization routines. Use Value: OTP Security ID enables hardware-rooted authentication; write lock-down prevents unauthorized modification of calibration tables post-deployment. |
| Medical Diagnostic Instrument Logging | Smart Energy Meter Data Buffer |
Use Scenario: Capturing time-stamped diagnostic waveforms and event logs in portable ultrasound or ECG devices requiring long-term data integrity. IC Role / Device Role / Timing Role: High-endurance data logger with >100-year retention - preserves audit trails across device lifetime. Use Value: 100,000-cycle endurance and low active current (15 mA @ 104 MHz) extend battery life while maintaining reliable storage for regulatory compliance records. | Use Scenario: Buffering interval-based consumption data in ANSI C12.22-compliant smart meters with periodic wireless upload. IC Role / Device Role / Timing Role: Low-power, sector-erasable nonvolatile memory supporting frequent small writes and infrequent bulk uploads. Use Value: 15 µA standby current minimizes meter self-consumption; uniform 4-Kbyte sectors allow efficient wear leveling across 10+ year deployment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q64JVSIQ | 64 Mbit SPI-only (no SQI), 133 MHz max, 2.7V–3.6V, same 8-pin SOIC/WSON packages | Lacks quad-I/O acceleration and hardware HOLD#/WP# flexibility; no OTP Security ID | Choose when SQI bandwidth is unnecessary and cost-sensitive SPI-only designs dominate |
| Cypress S25FL164K0XMFI010 | 64 Mbit, 85 MHz max, supports both SPI and QPI modes, 2.7V–3.6V, 8-pin SOIC/WSON | QPI mode requires different command set; no dedicated Security ID OTP area; different block protection granularity | Prefer when existing Cypress QPI ecosystem integration exists and Security ID is not required |
Compared with W25Q64JVSIQ and S25FL164K0XMFI010, the SST26VF064B-104I/WF70S delivers superior bandwidth via native SQI support, integrated hardware write protection with configurable pin roles, and factory-programmed cryptographic identity - making it optimal for secure, high-performance embedded boot and logging where deterministic timing and tamper resistance are mandatory.
Availability
SST26VF064B-104I/WF70S is available at Aetrix Electronics and suitable for industrial PLC firmware storage, automotive ADAS boot memory, medical diagnostic instrument logging, and smart energy meter data buffering requiring stable component supply across multi-year production cycles.
Supply support for SST26VF064B-104I/WF70S includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontroller, analog, FPGA, and memory solutions, serving industrial, automotive, communications, and consumer markets with vertically integrated silicon and software platforms.
The SST26VF064B-104I/WF70S belongs to Microchip's Serial Quad I/O™ Flash family, engineered specifically for systems demanding high-speed code execution, robust data integrity, and hardware-enforced security in space-constrained embedded applications.
FAQ
What is the default I/O configuration mode for SST26VF064B-104I/WF70S at power-up?
The SST26VF064B-104I/WF70S powers up with the I/O Configuration (IOC) bit set to '0', enabling WP# and HOLD# pins for SPI single/dual-bit operation and disabling SIO2/SIO3 for quad mode. This distinguishes it from the SST26VF064BA variant, which defaults to IOC=1. The IOC bit must be explicitly written to '1' before issuing SQI-specific commands like SQOR (6BH) or SQIOR (EBH).
Does SST26VF064B-104I/WF70S support both SPI and SQI protocols simultaneously?
No - the SST26VF064B-104I/WF70S operates in either SPI mode (using SI/SO or SI/SO/SIO2/SIO3 in dual/quad configurations) or SQI mode (using SIO[3:0] for all data), but not both concurrently. Mode selection is controlled by the IOC bit and command set: SPI commands (e.g., 03H, 0BH) function in SPI mode, while SQI commands (e.g., 0CH) require prior IOC=1 setting and operate only in SQI mode.
How does hardware write protection work on SST26VF064B-104I/WF70S?
Hardware write protection on the SST26VF064B-104I/WF70S is enabled when WPEN=1 (nonvolatile) and WP# is driven low, restricting writes to the Block Protection and Configuration registers only. The WP# pin is functional only in SPI single/dual-bit read mode with IOC=0. Once the Write Protection Lock-Down (WPLD) bit is set, even a low WP# signal cannot override the locked state - requiring a power cycle to clear WPLD.
What is the purpose of the Security ID feature in SST26VF064B-104I/WF70S?
The Security ID in SST26VF064B-104I/WF70S provides a 2-Kbyte dedicated area comprising a factory-programmed 64-bit unique identifier (immutable) and a user-programmable segment. It supports secure boot authentication and device binding via the PSID (Program Security ID) and LSID (Lockout Security ID) commands. Once LSID executes, the entire Security ID space becomes permanently read-only - preventing tampering with cryptographic keys or identifiers stored therein.
Can SST26VF064B-104I/WF70S perform erase or program operations while servicing another memory request?
Yes - the SST26VF064B-104I/WF70S supports Write Suspend, allowing an active Program or Erase operation to be paused via command so the host can read from or write to a different block/sector. Status bits WSP (Write Suspend Program) and WSE (Write Suspend Erase) in the STATUS register indicate suspension state. Resuming the suspended operation restores full throughput without data loss or re-initialization.
SST26VF064B-104I/WF70S Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- SST26 SQI®
- Package/Case:
- Die
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 64Mbit
- Memory Organization:
- 8M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 1.5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- Wafer
SST26VF064B-104I/WF70S FAQ
1.How can I place an order for SST26VF064B-104I/WF70S through Aetrix?
Please submit a Request for Quotation (RFQ) for SST26VF064B-104I/WF70S on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SST26VF064B-104I/WF70S reliable?
The price and inventory of SST26VF064B-104I/WF70S are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SST26VF064B-104I/WF70S is usually 5 days.
3.What payment methods are accepted for SST26VF064B-104I/WF70S?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SST26VF064B-104I/WF70S transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SST26VF064B-104I/WF70S?
SST26VF064B-104I/WF70S orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SST26VF064B-104I/WF70S order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SST26VF064B-104I/WF70S?
For technical support, including SST26VF064B-104I/WF70S datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SST26VF064B-104I/WF70S requirements.
6.How does Aetrix verify that SST26VF064B-104I/WF70S is sourced from the original manufacturer or authorized distributors?
All SST26VF064B-104I/WF70S products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SST26VF064B-104I/WF70S meets industry standards.
7.What is the process for return or replacement of SST26VF064B-104I/WF70S?
All SST26VF064B-104I/WF70S units undergo pre-shipment inspection (PSI). If there is an issue with SST26VF064B-104I/WF70S, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SST26VF064B-104I/WF70S part is unused and in its original packaging.
Return procedure for SST26VF064B-104I/WF70S:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SST26VF064B-104I/WF70S Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

