Microchip Technology SST26VF064BAT-104I/SM
- Part No.:
- SST26VF064BAT-104I/SM
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
SST26VF064BAT-104I/SM.pdf
- Description:
- IC FLASH 64MBIT SPI/QUAD 8SOIJ
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SST26VF064BAT-104I/SM from Microchip Technology is a 64-Mbit Serial Quad I/O™ (SQI™) Flash memory IC designed for high-speed, low-power embedded code storage and data logging. It operates at 104 MHz (2.7V–3.6V), supports x1/x2/x4 SPI and SQI protocols, features uniform 4-Kbyte sectors and 64-Kbyte blocks, and delivers 100,000 program/erase cycles with >100-year data retention in industrial temperature range (–40°C to +85°C).
For engineers reviewing the SST26VF064BAT-104I/SM datasheet, SST26VF064BAT-104I/SM pinout, SST26VF064BAT-104I/SM application, or SST26VF064BAT-104I/SM equivalent, this device serves as a drop-in upgrade path from legacy SPI Flash in space-constrained, performance-sensitive applications including boot code storage, firmware updates, and configuration data retention.
Technical Context
The SST26VF064BAT-104I/SM implements a six-wire, 4-bit multiplexed I/O interface supporting both traditional SPI (Mode 0/3) and high-throughput SQI protocol-quadrupling data bandwidth at identical clock frequency. Its SuperFlash® technology enables single-supply operation (2.3V–3.6V), fast erase (18 ms sector, 35 ms chip), and flexible protection via volatile/nonvolatile block lock-down registers.
It integrates dual-mode I/O configuration (IOC bit-controlled), hardware write protection (WP#), hold functionality (HOLD#), and a 2-Kbyte Security ID with factory-programmed 64-bit unique identifier and user-programmable segment-all accessible via standardized command set including RDSR, WRSR, RDCR, EQIO, and PSID.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 64 Mbit (8 MByte) organized as 126 × 64-Kbyte blocks, eight 8-Kbyte parameter blocks, and two 32-Kbyte overlay blocks |
| Interface Protocol | Supports x1/x2/x4 SPI and 4-bit SQI; IOC bit selects between WP#/HOLD# (SPI) or SIO2/SIO3 (Quad) pin mapping |
| Max Clock Frequency | 104 MHz at 2.7V–3.6V supply; enables up to 416 MB/s effective throughput in Quad I/O mode |
| Erase Performance | Sector/Block Erase: 18 ms typical; Chip Erase: 35 ms typical-reducing firmware update latency in OTA systems |
| Data Retention & Endurance | Greater than 100 years retention; 100,000 program/erase cycles-suitable for long-life industrial controllers |
| Operating Temperature | Industrial grade: –40°C to +85°C-validated for deployment in automotive ECUs and industrial HMIs |
| Security Features | One-Time-Programmable (OTP) 2-Kbyte Security ID with 64-bit factory-unique ID and lockable user area |
Pinout & Package
Package: 8-contact WDFN (6 mm × 5 mm), RoHS-compliant, moisture sensitivity level (MSL) 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CE# | Chip Enable | Active-low selection signal; must remain low throughout command sequence and data transfer |
| SO/SIO1 | Serial Output / Quad I/O Line 1 | Default SPI output (SO); reconfigured as bidirectional SIO1 in Quad mode after EQIO command |
| WP#/SIO2 | Write Protect Input / Quad I/O Line 2 | In SPI mode: hardware write-protection control; in Quad mode: bidirectional SIO2 after IOC=1 |
| VSS | Ground | Reference ground for all digital and I/O circuits; requires low-impedance PCB connection |
| VDD | Power Supply | 2.3V–3.6V single supply; powers core logic, memory array, and I/O buffers |
| HOLD#/SIO3 | Hold Input / Quad I/O Line 3 | In SPI mode: pauses ongoing serial transaction; disabled in SQI mode; reconfigured as SIO3 after IOC=1 |
| SCK | Serial Clock | Provides timing reference; commands/data latched on rising edge; output shifted on falling edge |
| SI/SIO0 | Serial Input / Quad I/O Line 0 | Default SPI input (SI); becomes bidirectional SIO0 in Quad mode after IOC=1 and EQIO command |
Key Features
| Feature | Design Value |
|---|---|
| SuperFlash® Technology | Enables lower programming current and shorter erase time vs. conventional Flash-reducing total energy per operation |
| Flexible Block Protection | Per-block write/read lock with volatile (LBPR) and nonvolatile (nVWLDR) lock-down-securing boot code and calibration data |
| Write Suspend Capability | Allows interruption of active Program/Erase to service higher-priority read requests-critical for real-time systems |
| Security ID with OTP Segment | Factory-programmed 64-bit unique ID + 2-Kbyte user-programmable area-enabling secure device authentication and binding |
| Multi-Voltage Operation | 2.3V–3.6V supply range supports direct interfacing with 2.5V and 3.3V host MCUs without level-shifting |
Applications
| Boot Code Storage | Firmware Over-the-Air (OTA) Updates |
|---|---|
Use Scenario: Storing primary bootloader and application firmware in microcontroller-based edge devices requiring cold-start reliability. IC Role / Device Role / Timing Role: Nonvolatile code storage with fast random read access and deterministic erase timing for verified firmware loading. Use Value: 104 MHz Quad I/O interface reduces boot time by ~4× versus standard SPI Flash; 100K-cycle endurance supports field firmware patching over 10+ years. | Use Scenario: Hosting differential firmware images in connected gateways where partial updates must complete reliably despite power interruptions. IC Role / Device Role / Timing Role: Dual-bank capable storage with suspend/resume for atomic image swap during power-loss-prone wireless transfers. Use Value: Write suspend feature allows immediate servicing of network stack interrupts mid-erase; 35 ms chip erase enables full-image rollback within <50 ms. |
| Industrial Configuration Data Logging | Automotive Diagnostic Memory |
Use Scenario: Recording sensor calibration coefficients, runtime fault logs, and maintenance history in programmable logic controllers (PLCs). IC Role / Device Role / Timing Role: High-reliability parameter storage with individual 8-Kbyte block protection to prevent accidental overwrite of critical settings. Use Value: Eight dedicated 8-Kbyte parameter blocks support independent read/write lock; >100-year data retention ensures log integrity across equipment lifetime. | Use Scenario: Storing ECU diagnostic trouble codes (DTCs), freeze frame data, and software version identifiers compliant with UDS (ISO 14229). IC Role / Device Role / Timing Role: AEC-Q100 Grade 2 qualified nonvolatile memory with hardware write protection for safety-critical diagnostic records. Use Value: WP# pin + nVWLDR lock-down prevents unauthorized DTC clearing; industrial temperature rating ensures operation under hood conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial Flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q64JWSSIQ | 64 Mbit, 133 MHz Quad SPI, no SQI mode; lacks Security ID and nonvolatile lock-down | Better raw speed but no OTP security ID or permanent block lock-down capability | Select when maximum read throughput is prioritized over cryptographic binding or tamper-proof configuration storage |
| Cypress S25FL164K0XMFI010 | 64 Mbit, 85 MHz Quad SPI, supports HyperBus but not SQI; includes 128-byte OTP security register | Lower max frequency; OTP area smaller (128 B vs. 2 KB); no nVWLDR for block-level permanent lock | Select when existing Cypress toolchain integration or HyperBus compatibility is required over SQI bandwidth or extended security ID capacity |
Compared with W25Q64JWSSIQ and S25FL164K0XMFI010, the SST26VF064BAT-104I/SM uniquely combines 104 MHz SQI throughput, 2-Kbyte OTP Security ID with factory-unique 64-bit ID, and nonvolatile write-lock lock-down for individual 4-Kbyte sectors-making it optimal for secure, high-speed embedded boot and update architectures.
Availability
SST26VF064BAT-104I/SM is available at Aetrix Electronics and suitable for industrial automation controllers, automotive diagnostic modules, and IoT gateway firmware storage requiring stable component supply, long-term lifecycle support, and AEC-Q100 Grade 2 qualification.
Supply support for SST26VF064BAT-104I/SM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global provider of microcontrollers, analog components, Flash memory, and security solutions, serving industrial, automotive, and communications markets with vertically integrated silicon and development tools.
The SST26VF064BAT-104I/SM belongs to Microchip's Serial Quad I/O™ Flash family, engineered specifically for high-bandwidth, low-pin-count code execution and secure firmware storage in resource-constrained embedded systems.
FAQ
What is the default I/O configuration mode for SST26VF064BAT-104I/SM at power-up?
The SST26VF064BAT-104I/SM ships in SST26VF064BA variant configuration: IOC bit defaults to '1', disabling WP# and HOLD# pins and enabling SIO2/SIO3 for Quad I/O operation. This allows immediate use of SQI commands like SQOR (6BH) and SQIOR (EBH) without initial configuration-unlike the SST26VF064B variant which defaults to SPI mode with WP#/HOLD# enabled.
Does SST26VF064BAT-104I/SM support both SPI and SQI protocols simultaneously?
No. The SST26VF064BAT-104I/SM operates in either SPI mode (x1/x2/x4) or SQI mode-not concurrently. Mode selection is controlled by the IOC bit in the Configuration register: IOC = 0 enables SPI with WP#/HOLD#; IOC = 1 enables Quad I/O with SIO2/SIO3. Switching requires issuing the EQIO command and reconfiguring pin functions.
How is hardware write protection implemented on SST26VF064BAT-104I/SM?
Hardware write protection on SST26VF064BAT-104I/SM uses the WP# pin in conjunction with the WPEN bit (nonvolatile) and IOC bit. When IOC = 0 and WPEN = 1, pulling WP# low disables writes to the Block Protection and Configuration registers. Since SST26VF064BAT-104I/SM defaults to IOC = 1, WP# is disabled at power-up unless explicitly reconfigured via WRSR.
What is the purpose and behavior of the Security ID feature in SST26VF064BAT-104I/SM?
The SST26VF064BAT-104I/SM includes a 2-Kbyte Security ID (Sec ID) with a factory-programmed 64-bit unique identifier and a user-programmable segment. The LSID command permanently locks the entire Sec ID space-preventing further writes. Once locked, the SEC bit in the STATUS register remains '1' permanently, ensuring immutable device identity for secure boot and anti-cloning applications.
Can SST26VF064BAT-104I/SM perform erase or program operations while another memory region is being read?
Yes. The SST26VF064BAT-104I/SM supports Write Suspend: an active Program or Erase operation can be suspended using the SUSPEND command, allowing immediate read access to any other block or sector. Resuming the suspended operation restores full throughput-enabling deterministic real-time response in multitasked embedded firmware.
SST26VF064BAT-104I/SM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- SST26 SQI®
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 64Mbit
- Memory Organization:
- 8M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 1.5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIJ
SST26VF064BAT-104I/SM FAQ
1.How can I place an order for SST26VF064BAT-104I/SM through Aetrix?
Please submit a Request for Quotation (RFQ) for SST26VF064BAT-104I/SM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SST26VF064BAT-104I/SM reliable?
The price and inventory of SST26VF064BAT-104I/SM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SST26VF064BAT-104I/SM is usually 5 days.
3.What payment methods are accepted for SST26VF064BAT-104I/SM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SST26VF064BAT-104I/SM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SST26VF064BAT-104I/SM?
SST26VF064BAT-104I/SM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SST26VF064BAT-104I/SM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SST26VF064BAT-104I/SM?
For technical support, including SST26VF064BAT-104I/SM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SST26VF064BAT-104I/SM requirements.
6.How does Aetrix verify that SST26VF064BAT-104I/SM is sourced from the original manufacturer or authorized distributors?
All SST26VF064BAT-104I/SM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SST26VF064BAT-104I/SM meets industry standards.
7.What is the process for return or replacement of SST26VF064BAT-104I/SM?
All SST26VF064BAT-104I/SM units undergo pre-shipment inspection (PSI). If there is an issue with SST26VF064BAT-104I/SM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SST26VF064BAT-104I/SM part is unused and in its original packaging.
Return procedure for SST26VF064BAT-104I/SM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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