My Inquiry
My Account
Microchip Technology SST26VF080AT-80E/MF
- Part No.:
- SST26VF080AT-80E/MF
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
SST26VF080AT-80E/MF.pdf
- Description:
- IC FLASH 8MBIT SPI/QUAD 8WDFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,942
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SST26VF080AT-80E/MF from Microchip Technology is an 8-Mbit Serial Quad I/O™ (SQI™) Flash memory IC designed for high-speed, low-power embedded code storage and data logging. It operates at 2.3V–3.6V, supports 80 MHz max clock frequency (Extended temperature), features uniform 4-Kbyte sectors and 32/64-Kbyte overlay blocks, and delivers 100,000 program/erase cycles with >100-year data retention. It is used in automotive infotainment boot memory and industrial PLC firmware storage.
For engineers reviewing the SST26VF080AT-80E/MF datasheet, SST26VF080AT-80E/MF pinout, SST26VF080AT-80E/MF application, or SST26VF080AT-80E/MF equivalent, key selection criteria include SQI vs. SPI mode compatibility, 80 MHz timing at extended temperature, WDFN-8 (6×5 mm) package footprint, hardware write protection via WP# pin, and OTP Security ID support for secure firmware binding.
Technical Context
The SST26VF080AT-80E/MF implements a six-wire, 4-bit multiplexed I/O interface (SIO[3:0]) supporting both legacy SPI (x1/x2) and high-throughput SQI protocols. Its SuperFlash® split-gate cell technology enables fast erase (20 ms sector, 40 ms chip) and low active current (15 mA @ 80 MHz) while maintaining single-supply operation.
It features dual-mode pin functionality: RST#/HOLD#/SIO3 and WP#/SIO2 are configurable via Configuration register bits (RSTHLD, IOC); burst modes include continuous linear and wrap-around (8/16/32/64-byte); and end-of-write detection uses BUSY bit polling in the STATUS register.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 8 Mbit (1 Mbyte), organized as 256 × 4-Kbyte sectors |
| Interface Protocol | Serial Quad I/O™ (SQI) and SPI (Mode 0/3, x1/x2/x4), backward-compatible command set |
| Max Clock Frequency | 80 MHz (2.3V–3.6V, Extended temp: –40°C to +125°C) |
| Erase Performance | 20 ms typical sector erase (4 Kbyte), 40 ms typical chip erase |
| Write Endurance | 100,000 program/erase cycles minimum per sector |
| Data Retention | Greater than 100 years at +85°C |
| Supply Voltage | 2.3V–3.6V single supply; no VCC/VIO separation required |
| Security Feature | 2-Kbyte OTP Security ID: 128-bit factory-unique ID + user-programmable area |
Pinout & Package
Package: 8-contact WDFN (6 mm × 5 mm, 0.5 mm pitch), RoHS-compliant, moisture sensitivity level (MSL) 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CE# | Chip Enable | Active-low enable for all serial commands; must remain low during full command sequence |
| SIO[0] (SI) | Serial Data Input | Default SPI input pin; latched on rising SCK edge; multiplexed as SIO0 in SQI mode |
| SIO[1] (SO) | Serial Data Output | Default SPI output pin; driven on falling SCK edge; multiplexed as SIO1 in SQI mode |
| SIO[2] (WP#) | Write-Protect / I/O | Hardware write-protection control in SPI mode; becomes SIO2 in SQI mode when IOC=1 |
| SIO[3] (RESET#/HOLD#) | Reset or Hold Control / I/O | Configurable via RSTHLD bit; RESET# active-low hardware reset (SPI only); HOLD# pauses communication (SPI only) |
| SCK | Serial Clock | Timing reference; data sampled on rising edge (input), shifted out on falling edge (output) |
| VDD | Power Supply | 2.3V–3.6V core supply; powers internal logic and memory array |
| VSS | Ground | Reference ground for all I/O and internal circuitry |
Key Features
| Feature | Design Value |
|---|---|
| Quad I/O Interface | 4-bit multiplexed SIO[3:0] enables 4× throughput vs. standard SPI at same clock frequency |
| Flexible Erase Architecture | Uniform 4-Kbyte sectors + 32-Kbyte and 64-Kbyte overlay blocks allow granular firmware updates |
| Write-Suspend Capability | Interrupt active program/erase to service higher-priority read requests without data corruption |
| OTP Security ID | Factory-programmed 128-bit unique ID + 2-Kbyte user area enables secure boot authentication and device binding |
| Automotive Qualification | AEC-Q100 Grade 1 qualified (–40°C to +125°C), suitable for engine control and ADAS firmware storage |
| Low-Power Active Mode | 15 mA typical read current at 80 MHz enables energy-efficient operation in battery-backed systems |
Applications
| Automotive Infotainment Boot Memory | Industrial PLC Firmware Storage |
|---|---|
Use Scenario: Storing boot code and OS kernel for head-unit microcontrollers requiring fast, reliable startup after cold start. IC Role / Device Role / Timing Role: Nonvolatile code storage with 80 MHz SQI read speed and AEC-Q100 qualification for under-hood temperature resilience. Use Value: Enables sub-100 ms firmware load time and eliminates risk of corruption during vehicle power cycling due to 100,000-cycle endurance and >100-year retention. | Use Scenario: Holding field-upgradable ladder logic and configuration data in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Secure, long-life data logger and firmware repository with write-suspend capability to avoid interrupting real-time I/O scanning. Use Value: Supports over-the-air firmware updates without halting machine operation, leveraging 4-Kbyte sector erase granularity and OTP Security ID for update integrity verification. |
| Medical Diagnostic Device Parameter Storage | Smart Energy Meter Calibration Data |
Use Scenario: Retaining calibration coefficients, sensor offset tables, and regulatory audit logs in portable ultrasound and ECG analyzers. IC Role / Device Role / Timing Role: Tamper-resistant, high-reliability nonvolatile memory with 2-Kbyte OTP Security ID for FDA 21 CFR Part 11 compliance. Use Value: Ensures traceable, unalterable calibration history across device lifetime, backed by >100-year data retention and hardware write protection. | Use Scenario: Storing metrology calibration constants, tariff tables, and tamper-event logs in ANSI C12.20-certified smart electricity meters operating in outdoor enclosures. IC Role / Device Role / Timing Role: Extended-temperature (–40°C to +125°C) Flash memory with 80 MHz read performance for rapid meter initialization at power-on. Use Value: Guarantees accurate billing data persistence across 20+ year field life, validated by 100,000-cycle endurance and AEC-Q100 reliability testing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial Flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q80DVSSIG | 8-Mbit SPI-only (no SQI), 104 MHz max, SOIC-8 package only, no OTP Security ID | Lacks SQI bandwidth and security features; suitable for cost-sensitive, non-automotive designs | Select if SQI interface and AEC-Q100 qualification are unnecessary and SOIC-8 footprint is preferred |
| Cypress S25FL008KAGMFI010 | 8-Mbit Quad SPI (QSPI), 104 MHz, WSON-8 (6×5 mm), no OTP Security ID, no write-suspend | Supports QSPI but not SQI protocol; lacks Security ID and suspend/resume functionality | Choose when QSPI compatibility suffices and advanced security or interruptible writes are not required |
Compared with W25Q80DVSSIG and S25FL008KAGMFI010, the SST26VF080AT-80E/MF uniquely combines AEC-Q100 qualification, SQI protocol acceleration, OTP Security ID, and write-suspend-making it optimal for automotive and safety-critical industrial firmware where throughput, security, and operational flexibility are jointly required.
Availability
SST26VF080AT-80E/MF is available at Aetrix Electronics and suitable for automotive infotainment, industrial PLC firmware, and medical diagnostic device applications requiring stable component supply, extended-temperature operation, and secure boot capabilities.
Supply support for SST26VF080AT-80E/MF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontroller, analog, FPGA, and memory solutions, headquartered in Chandler, Arizona, with global design, manufacturing, and sales operations.
The SST26VF080AT-80E/MF belongs to Microchip's Serial Quad I/O™ Flash memory product line, engineered specifically for high-reliability, high-speed embedded code execution and secure firmware storage in automotive, industrial, and medical systems.
FAQ
What is the maximum clock frequency supported by SST26VF080AT-80E/MF at extended temperature?
The SST26VF080AT-80E/MF supports up to 80 MHz maximum clock frequency when operating across the extended temperature range of –40°C to +125°C, under 2.3V–3.6V supply conditions. This rating is validated per AEC-Q100 Grade 1 requirements and applies to both SPI and SQI read operations. The 80 MHz limit ensures timing margin and signal integrity in thermally demanding automotive and industrial environments where the SST26VF080AT-80E/MF is commonly deployed.
Does SST26VF080AT-80E/MF support true Quad I/O (QIO) or only Serial Quad I/O (SQI)?
The SST26VF080AT-80E/MF implements Serial Quad I/O™ (SQI), a proprietary Microchip protocol using four multiplexed bidirectional I/O lines (SIO[3:0]) for command, address, and data transfer - distinct from standard Quad SPI (QSPI). Unlike QSPI, SQI requires explicit EQIO (38H) command activation and supports continuous linear burst reads. The SST26VF080AT-80E/MF does not support JEDEC-standard QSPI commands like 4-4-4 or 0-4-4, and its SQI mode is incompatible with generic QSPI controllers without firmware adaptation.
How is hardware write protection implemented on SST26VF080AT-80E/MF?
Hardware write protection on SST26VF080AT-80E/MF is controlled by the WP# pin in conjunction with the WPEN and IOC bits in the Configuration register. When IOC = 0 (default), WP# functions as a hardware write-protect input; when WPEN = 1 and WP# is driven low, it locks the Block Protection Lock-down (BPL) bit and prevents modification of BP0–BP3 in the STATUS register. The SST26VF080AT-80E/MF ships with WPEN = 0 by default, disabling WP# functionality until explicitly enabled via Configuration register write.
Can SST26VF080AT-80E/MF be used as a direct replacement for standard SPI Flash devices?
Yes, the SST26VF080AT-80E/MF is fully backward-compatible with standard SPI Flash devices at power-on reset: it defaults to SPI x1 mode and supports all common SPI opcodes (03H, 0BH, 20H, D8H, etc.). No hardware changes are needed to integrate the SST26VF080AT-80E/MF into existing SPI-based designs. However, to leverage SQI performance or advanced features like write-suspend or Security ID, firmware modifications and proper Configuration register setup (IOC, RSTHLD) are required.
What is the purpose and structure of the Security ID feature in SST26VF080AT-80E/MF?
The SST26VF080AT-80E/MF includes a 2-Kbyte OTP Security ID space comprising a factory-programmed 128-bit unique identifier (immutable) and a user-programmable 2-Kbyte region. The Security ID is accessed via PSID (A5H), RSID (88H), and LSID (85H) commands. Once locked with LSID, the entire Security ID space becomes read-only. This feature enables cryptographic binding of firmware images to specific hardware units - a critical requirement for secure boot in automotive and medical applications using the SST26VF080AT-80E/MF.
SST26VF080AT-80E/MF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- SST26 SQI®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 8Mbit
- Memory Organization:
- 1M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 80 MHz
- Write Cycle Time - Word, Page:
- 1.5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WDFN (5x6)
SST26VF080AT-80E/MF FAQ
1.How can I place an order for SST26VF080AT-80E/MF through Aetrix?
Please submit a Request for Quotation (RFQ) for SST26VF080AT-80E/MF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SST26VF080AT-80E/MF reliable?
The price and inventory of SST26VF080AT-80E/MF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SST26VF080AT-80E/MF is usually 5 days.
3.What payment methods are accepted for SST26VF080AT-80E/MF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SST26VF080AT-80E/MF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SST26VF080AT-80E/MF?
SST26VF080AT-80E/MF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SST26VF080AT-80E/MF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SST26VF080AT-80E/MF?
For technical support, including SST26VF080AT-80E/MF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SST26VF080AT-80E/MF requirements.
6.How does Aetrix verify that SST26VF080AT-80E/MF is sourced from the original manufacturer or authorized distributors?
All SST26VF080AT-80E/MF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SST26VF080AT-80E/MF meets industry standards.
7.What is the process for return or replacement of SST26VF080AT-80E/MF?
All SST26VF080AT-80E/MF units undergo pre-shipment inspection (PSI). If there is an issue with SST26VF080AT-80E/MF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SST26VF080AT-80E/MF part is unused and in its original packaging.
Return procedure for SST26VF080AT-80E/MF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SST26VF080AT-80E/MF Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
