Microchip Technology SST26WF064C-104I/TD
- Part No.:
- SST26WF064C-104I/TD
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
SST26WF064C-104I/TD.pdf
- Description:
- IC FLASH 64MBIT SPI/QUAD 24TBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SST26WF064C-104I/TD from Microchip Technology is a 1.8V, 64 Mbit Serial Quad I/O (SQI) flash memory IC designed for high-speed, low-power embedded code storage and data logging. It delivers 104 MHz single-data-rate (SDR) clock performance, supports x1/x2/x4 SPI and SQI protocols, and features uniform 4 KByte sectors with flexible block protection - deployed in industrial-grade microcontroller boot memory and FPGA configuration storage.
For engineers reviewing the SST26WF064C-104I/TD datasheet, SST26WF064C-104I/TD pinout, SST26WF064C-104I/TD application, or SST26WF064C-104I/TD equivalent, key selection criteria include its 1.65–1.95 V single-supply operation, 100,000-cycle endurance, JEDEC SFDP compliance, hardware reset capability, and configurable WP#/HOLD#/RESET# multiplexed pin functionality across WDFN/SOIJ/SOIC/TBGA packages.
Technical Context
The SST26WF064C-104I/TD implements a six-wire SQI interface (SCK, CE#, SIO[3:0]) with dual-mode support: default SPI mode (SI/SO) at power-up and configurable quad I/O mode via EQIO command. Its SuperFlash® split-gate cell architecture enables faster erase (18 ms sector, 35 ms chip) and lower active current (15 mA @ 104 MHz) versus conventional NOR flash.
It integrates three protection layers: software-configurable Block-Protection Register (144-bit), volatile Write-Protection Lock-Down (LBPR), and non-volatile Write-Lock Lock-Down (nVWLDR). The device also embeds a 2 KByte Security ID with factory-programmed 64-bit unique identifier and user-programmable OTP area, accessible via PSID/LSID commands.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 64 Mbit (8 MByte) organized as 126 × 64 KByte blocks + parameter overlay blocks |
| Supply Voltage | 1.65–1.95 V - enables direct interfacing with 1.8 V logic without level shifters |
| Max Clock Frequency | 104 MHz SDR / 50 MHz DTR - delivers up to 416 MB/s effective throughput in x4 SQI mode |
| Endurance & Retention | 100,000 program/erase cycles minimum; >100 years data retention at 85°C |
| Power Consumption | 15 mA active read (typ), 10 µA standby, 2.5 µA deep power-down - critical for battery-backed systems |
| Erase Performance | Sector/Block erase: 18 ms typ (25 ms max); chip erase: 35 ms typ (50 ms max) |
| Interface Protocols | Full SPI Mode 0/3 compatibility + SQI (x4) + DTR support - ensures backward compatibility and upgrade path |
Pinout & Package
Package: 8-contact WDFN (6 mm × 5 mm), RoHS-compliant, industrial temperature range (−40°C to +85°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CE# | Chip Enable | Active-low enable for serial command execution; must remain low during full command/data sequence |
| SIO0 (SI) | Serial Data Input (SPI default) | Latches input on rising SCK edge; functions as SI in SPI mode, SIO0 in SQI mode |
| SIO1 (SO) | Serial Data Output (SPI default) | Drives output on falling SCK edge; functions as SO in SPI mode, SIO1 in SQI mode |
| WP# | Write Protect Input | Hardware lock for Block-Protection/Configuration registers when IOC=0 & WPEN=1 |
| VSS | Ground | Reference return path for all I/O and core circuitry |
| VDD | Power Supply | 1.65–1.95 V supply for core and I/O - no separate VCCIO required |
| RESET#/HOLD# | Multiplexed Reset/Hold | Configurable via RSTHLD bit: RESET# (all modes, 16-SOIC/TBGA dedicated) or HOLD# (SPI only, 8-pin packages) |
| SCK | Serial Clock | Timing reference; sampled on rising edge (input), drives output on falling edge |
Key Features
| Feature | Design Value |
|---|---|
| Quad I/O (SQI) Interface | Four multiplexed I/O lines (SIO[3:0]) enabling 4× bandwidth vs. standard SPI at same clock frequency |
| Flexible Erase Architecture | Uniform 4 KByte sectors + eight 8 KByte parameter blocks + two 32 KByte + one 32 KByte top/bottom overlays |
| Three-Tier Protection Scheme | Software BPR + volatile LBPR + non-volatile nVWLDR - enables secure, field-upgradable memory partitioning |
| Security ID with OTP | 2 KByte space: 64-bit factory-unique ID + user-programmable area, lockable via LSID command |
| Write-Suspend Capability | Pause ongoing Program/Erase to service urgent reads from other blocks - essential for real-time firmware updates |
| JEDEC SFDP Compliance | Standardized parameter table enables automatic driver initialization and protocol negotiation in modern bootloaders |
Applications
| Microcontroller Boot Memory | FPGA Configuration Storage |
|---|---|
|
Use Scenario: Storing boot code for ARM Cortex-M7 or RISC-V SoCs requiring fast, reliable startup from external flash. IC Role / Device Role / Timing Role: Primary non-volatile code storage accessed via XIP-capable SPI/QPI controllers during cold boot and warm reset sequences. Use Value: 104 MHz SDR clock and continuous linear burst mode reduce boot time by >35% vs. legacy 50 MHz SPI flash; 1.8 V operation eliminates level-shifting overhead. |
Use Scenario: Holding bitstream images for Xilinx Artix-7 or Intel Cyclone V FPGAs in industrial control PLCs. IC Role / Device Role / Timing Role: Configuration memory mapped to FPGA's master SPI interface during power-on initialization and partial reconfiguration. Use Value: Uniform 4 KByte sectors allow precise bitstream partitioning; write-suspend enables dynamic partial reconfiguration without halting system operation. |
| Secure Firmware Update Storage | Industrial Data Logger Buffer |
|
Use Scenario: Storing signed firmware images and cryptographic keys in medical IoT gateways with regulatory audit requirements. IC Role / Device Role / Timing Role: Tamper-resistant storage for OTA update payloads and root-of-trust metadata, accessed via secure bootloader. Use Value: Non-volatile nVWLDR permanently locks critical security partitions; 64-bit factory ID enables device-specific key binding and anti-cloning. |
Use Scenario: Cyclic buffering of sensor telemetry (temperature, vibration, pressure) in predictive maintenance edge nodes. IC Role / Device Role / Timing Role: High-endurance data archive supporting frequent small-block writes and background wear leveling. Use Value: 100,000-cycle endurance and 2.5 µA deep power-down extend battery life beyond 5 years in sealed deployments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q64JVSSIQ | 3.3 V supply only; no SQI/DTR; 80 MHz max clock; lacks Security ID and nVWLDR | Suitable for cost-sensitive 3.3 V designs without security or ultra-low-power needs | Select if voltage compatibility and basic SPI suffice; avoid for 1.8 V or secure boot use cases |
| Cypress S25FL164K0XMFI010 | 1.8 V supply; 80 MHz max; HyperBus interface (not SPI/SQI); no DTR or Security ID | Optimized for high-bandwidth XIP in automotive infotainment with parallel-like timing | Choose only when HyperBus controller is present; not drop-in compatible with SPI/SQI host interfaces |
Compared with W25Q64JVSSIQ and S25FL164K0XMFI010, the SST26WF064C-104I/TD uniquely combines 1.8 V operation, 104 MHz SQI speed, JEDEC SFDP, and multi-layer security - making it the only option among the three qualified for secure, low-voltage, high-throughput embedded boot and configuration.
Availability
SST26WF064C-104I/TD is available at Aetrix Electronics and suitable for industrial control systems, medical edge devices, and automotive telematics modules requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for SST26WF064C-104I/TD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and memory solutions, with global design centers and ISO 9001-certified manufacturing.
The SST26WF064C-104I/TD belongs to Microchip's Serial Quad I/O™ (SQI™) flash family, engineered specifically for high-reliability embedded systems demanding low-voltage operation, fast boot times, and robust firmware security.
FAQ
What is the operating voltage range for SST26WF064C-104I/TD?
The SST26WF064C-104I/TD operates exclusively within a 1.65 V to 1.95 V supply range - optimized for 1.8 V systems. It does not support 3.3 V operation, and applying voltage outside this window may cause functional failure or reduced reliability. This narrow range enables tighter power budgeting and eliminates need for external level shifters when interfacing with 1.8 V microcontrollers or FPGAs.
Does SST26WF064C-104I/TD support both SPI and SQI protocols?
Yes, SST26WF064C-104I/TD powers up in standard SPI mode (Mode 0 or 3) with SI/SO pins enabled, ensuring full backward compatibility. It transitions to SQI mode only after issuing the Enable Quad I/O (EQIO) command and setting the IOC bit - allowing seamless integration into legacy SPI designs while enabling bandwidth scaling where needed.
How does the Security ID feature work in SST26WF064C-104I/TD?
The SST26WF064C-104I/TD includes a 2 KByte Security ID space: 64 bits factory-programmed with a unique identifier (read-only), plus user-programmable OTP area. Users write via PSID command and permanently lock with LSID - after which SEC bit = 1 and no further writes are possible. Neither factory nor user areas can be erased, ensuring immutable device identity.
What package options are available for SST26WF064C-104I/TD?
The SST26WF064C-104I/TD is offered in four industrial-grade packages: 8-contact WDFN (6 mm × 5 mm), 8-lead SOIJ (5.28 mm), 16-lead SOIC (7.50 mm), and 24-ball TBGA (8 mm × 6 mm). All meet RoHS requirements and operate from −40°C to +85°C. The "/TD" suffix specifically denotes the 8-contact WDFN variant per Microchip's ordering nomenclature.
Can SST26WF064C-104I/TD perform simultaneous read and write operations?
No, SST26WF064C-104C-104I/TD does not support true concurrent read/write. However, it provides Write-Suspend functionality: an active Program or Erase operation can be paused using SUSPEND command, allowing immediate read access to other memory blocks - then resumed later. This enables deterministic latency handling in real-time firmware update scenarios.
SST26WF064C-104I/TD Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- SST26 SQI®
- Package/Case:
- 24-TBGA
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 64Mbit
- Memory Organization:
- 8M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 1.5ms
- Access Time:
- -
- Voltage - Supply:
- 1.65V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TBGA (6x8)
SST26WF064C-104I/TD FAQ
1.How can I place an order for SST26WF064C-104I/TD through Aetrix?
Please submit a Request for Quotation (RFQ) for SST26WF064C-104I/TD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SST26WF064C-104I/TD reliable?
The price and inventory of SST26WF064C-104I/TD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SST26WF064C-104I/TD is usually 5 days.
3.What payment methods are accepted for SST26WF064C-104I/TD?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SST26WF064C-104I/TD transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SST26WF064C-104I/TD?
SST26WF064C-104I/TD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SST26WF064C-104I/TD order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SST26WF064C-104I/TD?
For technical support, including SST26WF064C-104I/TD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SST26WF064C-104I/TD requirements.
6.How does Aetrix verify that SST26WF064C-104I/TD is sourced from the original manufacturer or authorized distributors?
All SST26WF064C-104I/TD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SST26WF064C-104I/TD meets industry standards.
7.What is the process for return or replacement of SST26WF064C-104I/TD?
All SST26WF064C-104I/TD units undergo pre-shipment inspection (PSI). If there is an issue with SST26WF064C-104I/TD, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SST26WF064C-104I/TD part is unused and in its original packaging.
Return procedure for SST26WF064C-104I/TD:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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