Microchip Technology SST26WF064CT-104I/MF
- Part No.:
- SST26WF064CT-104I/MF
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
SST26WF064CT-104I/MF.pdf
- Description:
- IC FLASH 64MBIT SPI/QUAD 8WDFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SST26WF064CT-104I/MF from Microchip Technology is a 1.8V, 64 Mbit Serial Quad I/O™ (SQI™) flash memory IC designed for high-speed, low-power embedded code storage and data logging. It delivers 104 MHz single-data-rate (SDR) clock performance, supports x1/x2/x4 SPI and SQI protocols, and features uniform 4 KByte sectors with flexible block protection - deployed in industrial-grade IoT gateways, automotive telematics boot memory, and medical device firmware storage.
For engineers reviewing the SST26WF064CT-104I/MF datasheet, SST26WF064CT-104I/MF pinout, SST26WF064CT-104I/MF application, or SST26WF064CT-104I/MF equivalent, key selection criteria include its 1.65–1.95 V single-supply operation, 100,000-cycle endurance, JEDEC SFDP compliance, hardware reset capability, and WDFN-8 (6 mm × 5 mm) package compatibility with space-constrained PCB layouts.
Technical Context
The SST26WF064CT-104I/MF implements a six-wire SQI interface (SCK, CE#, RESET#/HOLD#/SIO3, WP#/SIO2, SI/SIO0, SO/SIO1, VDD, VSS) enabling 4-bit multiplexed I/O transfers at up to 104 MHz SDR or 50 MHz DTR. Its SuperFlash® split-gate cell architecture achieves 18 ms typical sector erase and 256-byte page programming without external voltage boosting.
It operates in two configurable I/O modes: default SPI mode (SI/SO pins active, WP#/HOLD# functional) and SQI mode (SIO[3:0] enabled via IOC bit), with hardware reset support across all packages and software reset (66H/99H) universally available. The device integrates a 2 KByte OTP Security ID with factory-programmed 64-bit unique identifier and user-programmable segment.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 64 Mbit (8 MByte) organized as uniform 4 KByte sectors and configurable overlay blocks |
| Clock Frequency | 104 MHz max SDR; enables 416 MB/s theoretical throughput in x4 SQI mode |
| Supply Voltage | 1.65–1.95 V single supply; eliminates need for dual-voltage rails in ultra-low-power systems |
| Endurance & Retention | 100,000 program/erase cycles minimum; >100 years data retention at 85°C |
| Active Current | 15 mA typical @ 104 MHz; reduces thermal load in fanless edge controllers |
| Deep Power-Down | 2.5 µA typical; supports battery-backed firmware storage in always-on sensors |
| Security ID | 2 KByte OTP area: 64-bit factory-unique ID + user-programmable segment, lockable via LSID command |
Pinout & Package
Package: 8-contact WDFN (6 mm × 5 mm), RoHS-compliant, industrial temperature range (−40°C to +85°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: CE# | Chip Enable | Active-low chip select; must remain low throughout command/data sequences including write operations |
| 2: SO/SIO1 | Serial Output / Quad I/O Line 1 | Default SPI output (SO); becomes SIO1 in SQI mode after IOC=1 configuration |
| 3: WP#/SIO2 | Write Protect Input / Quad I/O Line 2 | Hardware write-protection enable (SPI mode only); reconfigured as SIO2 in SQI mode |
| 4: VSS | Ground | Reference return path for all I/O and core logic; requires low-impedance PCB plane |
| 5: VDD | Power Supply | 1.65–1.95 V core supply; decoupling capacitor mandatory per Microchip layout guidelines |
| 6: RESET#/HOLD#/SIO3 | Reset/Hold Control / Quad I/O Line 3 | Configurable via RSTHLD bit: RESET# (all packages), HOLD# (SPI only), or SIO3 (SQI only) |
| 7: SCK | Serial Clock | Timing reference for all serial transfers; supports Mode 0 (idle low) and Mode 3 (idle high) |
| 8: SI/SIO0 | Serial Input / Quad I/O Line 0 | Default SPI input (SI); becomes SIO0 in SQI mode after IOC=1 configuration |
Key Features
| Feature | Design Value |
|---|---|
| Quad I/O Interface | Enables 4× bandwidth vs. standard SPI at same clock frequency - critical for fast boot times in ARM Cortex-M7 applications |
| Flexible Block Protection | Independent write-lock/read-lock per 8 KByte parameter block and write-lock per 32/64 KByte overlay block, with non-volatile lock-down |
| Write-Suspend Capability | Allows interruption of ongoing erase/program to service higher-priority read requests - essential for real-time firmware updates |
| Dual-Transfer Rate (DTR) | Supports data sampling on both clock edges (50 MHz DTR = 200 Mbps effective rate), reducing timing margin pressure on high-speed PCBs |
| JEDEC SFDP Compliance | Enables automatic configuration by host bootloader without hard-coded parameters - simplifies BOM management across flash variants |
| Security ID with OTP Lock | Factory-unique 64-bit ID + user-programmable 2 KByte region, permanently lockable to prevent cloning or unauthorized firmware modification |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Memory |
|---|---|
|
Use Scenario: Storing certified control firmware in programmable logic controllers operating continuously in factory environments with wide temperature swings. IC Role / Device Role / Timing Role: Primary non-volatile code storage with guaranteed 100K-cycle endurance and >100-year data retention at 85°C. Use Value: Eliminates field failures due to premature wear-out; supports over-the-air (OTA) firmware updates without requiring external voltage pumps or complex wear-leveling firmware. |
Use Scenario: Holding boot code and safety-critical sensor calibration data in autonomous driving ECUs where power loss during update must not corrupt integrity. IC Role / Device Role / Timing Role: Secure, fast-access boot memory with hardware reset recovery and write-suspend to maintain system responsiveness during concurrent diagnostics. Use Value: Enables deterministic <100 ms boot time via 104 MHz SQI interface while preventing accidental overwrite of calibrated parameters using individual block protection. |
| Medical Infusion Pump Data Logging | Smart Energy Meter Firmware Vault |
|
Use Scenario: Recording dosage history and error logs in battery-powered infusion pumps requiring multi-year retention without maintenance. IC Role / Device Role / Timing Role: Low-power data logger with 2.5 µA deep power-down current and 4 KByte sector granularity for efficient log rotation. Use Value: Extends battery life beyond 5 years; leverages uniform sector erase to avoid write amplification and ensure predictable log write latency. |
Use Scenario: Storing encrypted meter firmware and tariff tables in utility-grade smart meters subject to rigorous tamper-resistance requirements. IC Role / Device Role / Timing Role: Secure firmware vault with 2 KByte OTP Security ID and permanent lock-down capability for regulatory audit trails. Use Value: Meets IEC 62443-3-3 SL2 requirements via factory-unique ID binding and irreversible lock-out of security-critical regions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q64JVSIQ | 3.3 V supply; no SQI interface; 80 MHz max clock; lacks Security ID and DTR mode | Requires level-shifting in 1.8 V systems; lower bandwidth limits boot speed in high-end MCUs | Select when cost sensitivity outweighs performance and security needs; verify voltage compatibility with host controller |
| Cypress S25FL164K0XMFI001 | 1.8 V supply; supports x4 Quad SPI but no SQI protocol; 80 MHz max clock; no OTP Security ID | Lacks multiplexed SQI pin mapping; cannot achieve 104 MHz SDR or 50 MHz DTR performance | Choose for legacy Quad SPI designs needing pin compatibility with Cypress portfolio; not suitable for new SQI-optimized layouts |
Compared with W25Q64JVSIQ and S25FL164K0XMFI001, the SST26WF064CT-104I/MF uniquely delivers 104 MHz SDR operation, integrated SQI protocol with pin-multiplexed I/O, and factory-programmed 64-bit Security ID - making it the only option among the three that satisfies simultaneous requirements for ultra-fast boot, minimal pin count, and cryptographic identity binding in industrial and automotive designs.
Availability
SST26WF064CT-104I/MF is available at Aetrix Electronics and suitable for industrial PLC firmware storage, automotive ADAS boot memory, and medical infusion pump data logging requiring stable component supply across extended product lifecycles.
Supply support for SST26WF064CT-104I/MF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and secure memory solutions with emphasis on long-lifecycle support and industrial reliability.
The SST26WF064CT-104I/MF belongs to Microchip's Serial Quad I/O™ (SQI™) flash family, engineered specifically for high-performance, low-voltage embedded systems demanding fast code execution, robust data integrity, and hardware-enforced security.
FAQ
What is the operating voltage range for the SST26WF064CT-104I/MF?
The SST26WF064CT-104I/MF operates from a single supply of 1.65 V to 1.95 V. This narrow 1.8 V nominal range eliminates the need for voltage translation in modern ultra-low-power SoC designs and ensures compatibility with 1.8 V I/O domains. Operation outside this range may cause unreliable read/write behavior or damage the device.
Does the SST26WF064CT-104I/MF support hardware reset across all package types?
Yes, the SST26WF064CT-104I/MF supports hardware reset in all packages. In 8-pin SOIJ and WDFN packages, the RESET#/HOLD#/SIO3 pin functions as RESET# when the RSTHLD bit is set to '1' in the Configuration register. In 16-lead SOIC and 24-ball TBGA packages, a dedicated RESET# pin provides unconditional hardware reset capability in all operating modes.
How does the Security ID feature work in the SST26WF064CT-104I/MF?
The SST26WF064CT-104I/MF includes a 2 KByte Security ID (Sec ID) area comprising a factory-programmed 64-bit unique identifier and a user-programmable segment. Users can write to the user area using the PSID command and permanently lock both segments using the LSID command - after which no further writes are possible, ensuring immutable device identity for anti-cloning and firmware binding.
Can the SST26WF064CT-104I/MF be used in both SPI and SQI modes simultaneously?
No, the SST26WF064CT-104I/MF operates exclusively in either SPI mode (default at power-up) or SQI mode, selected via the I/O Configuration (IOC) bit in the Configuration register. When IOC = 0, SI/SO/WP#/HOLD# are active; when IOC = 1, SIO[3:0] are enabled and WP#/HOLD# are disabled. Mode switching requires issuing the appropriate configuration command and is not dynamic during active transfers.
What is the significance of the "-104I/MF" suffix in SST26WF064CT-104I/MF?
The "-104I/MF" suffix indicates the device is rated for 104 MHz maximum clock frequency (104), industrial temperature range (−40°C to +85°C) (I), and packaged in an 8-contact WDFN (6 mm × 5 mm) with matte tin finish (MF). This specific variant guarantees full 104 MHz SDR performance and meets IPC/JEDEC moisture sensitivity level 3 (MSL3) handling requirements.
SST26WF064CT-104I/MF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- SST26 SQI®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 64Mbit
- Memory Organization:
- 8M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 1.5ms
- Access Time:
- -
- Voltage - Supply:
- 1.65V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WDFN (5x6)
SST26WF064CT-104I/MF FAQ
1.How can I place an order for SST26WF064CT-104I/MF through Aetrix?
Please submit a Request for Quotation (RFQ) for SST26WF064CT-104I/MF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SST26WF064CT-104I/MF reliable?
The price and inventory of SST26WF064CT-104I/MF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SST26WF064CT-104I/MF is usually 5 days.
3.What payment methods are accepted for SST26WF064CT-104I/MF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SST26WF064CT-104I/MF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SST26WF064CT-104I/MF?
SST26WF064CT-104I/MF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SST26WF064CT-104I/MF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SST26WF064CT-104I/MF?
For technical support, including SST26WF064CT-104I/MF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SST26WF064CT-104I/MF requirements.
6.How does Aetrix verify that SST26WF064CT-104I/MF is sourced from the original manufacturer or authorized distributors?
All SST26WF064CT-104I/MF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SST26WF064CT-104I/MF meets industry standards.
7.What is the process for return or replacement of SST26WF064CT-104I/MF?
All SST26WF064CT-104I/MF units undergo pre-shipment inspection (PSI). If there is an issue with SST26WF064CT-104I/MF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SST26WF064CT-104I/MF part is unused and in its original packaging.
Return procedure for SST26WF064CT-104I/MF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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