Microchip Technology SST26WF064CT-104I/SM
- Part No.:
- SST26WF064CT-104I/SM
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
SST26WF064CT-104I/SM.pdf
- Description:
- IC FLASH 64MBIT SPI/QUAD 8SOIJ
- Quantity:
- Payment:

- Shipping:

Inventory:4,819
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SST26WF064CT-104I/SM from Microchip Technology is a 1.8V, 64 Mbit Serial Quad I/O™ (SQI™) flash memory IC with uniform 4 KByte sectors, 104 MHz max clock frequency, and industrial temperature range (–40°C to +85°C). It supports x1/x2/x4 SPI protocols, Dual-Transfer Rate (DTR), and flexible block protection for embedded boot code and firmware storage in space-constrained MCU systems.
For engineers reviewing the SST26WF064CT-104I/SM datasheet, SST26WF064CT-104I/SM pinout, SST26WF064CT-104I/SM application, or SST26WF064CT-104I/SM equivalent, key selection criteria include single-supply 1.65–1.95V operation, 100,000-cycle endurance, 2.5 µA deep power-down current, JEDEC SFDP compliance, and WDFN-8 (6 mm × 5 mm) package compatibility with high-density PCB layouts.
Technical Context
The SST26WF064CT-104I/SM implements a six-wire, 4-bit multiplexed I/O interface supporting both legacy SPI (Mode 0/3) and high-speed SQI protocol - enabling quad-data-rate transfers without increasing pin count. Its SuperFlash® split-gate cell architecture delivers faster erase (18 ms sector, 35 ms chip) and lower program energy versus conventional NOR flash.
It integrates configurable I/O pins (SIO[3:0]), hardware reset (RESET#), hold (HOLD#), and write-protect (WP#) functions, all managed via non-volatile configuration register bits (IOC, WPEN, RSTHLD). The device defaults to SPI mode at power-up and requires explicit IOC=1 to enable SQI or DTR commands.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 64 Mbit (8 MByte) organized as uniform 4 KByte sectors and 64 KByte overlay blocks |
| Supply Voltage | 1.65–1.95 V - enables direct interfacing with 1.8V logic domains without level-shifting |
| Max Clock Frequency | 104 MHz (SPI/x4), 50 MHz (DTR) - supports up to 416 MB/s effective throughput in SQI mode |
| Endurance & Retention | 100,000 program/erase cycles minimum; >100 years data retention - suitable for field-upgradable firmware |
| Power Consumption | 15 mA active read (typ @ 104 MHz), 10 µA standby, 2.5 µA deep power-down - critical for battery-backed systems |
| Erase Performance | Sector/Block erase: 18 ms typ; Chip erase: 35 ms typ - reduces firmware update latency in OTA applications |
| Security Features | 2 KByte OTP Security ID (64-bit factory-unique + user-programmable), lockable via LSID command - supports secure boot authentication |
Pinout & Package
Package: 8-contact WDFN (6 mm × 5 mm), RoHS-compliant, moisture-sensitive level 3 (MSL3).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CE# | Chip Enable | Active-low chip select; must remain low during full command sequence including address/data transfer |
| SO/SIO1 | Serial Output / Quad I/O 1 | Default SPI output (SO); becomes bidirectional SIO1 in SQI mode after IOC=1 configuration |
| WP#/SIO2 | Write Protect / Quad I/O 2 | Hardware write-protection input in SPI mode; reconfigured as SIO2 in SQI mode when IOC=1 |
| VSS | Ground | Reference ground for all I/O and core circuitry; requires low-impedance PCB connection |
| VDD | Power Supply | 1.65–1.95 V supply; decoupling capacitor (≥1 µF) required within 10 mm of pin |
| RESET#/HOLD#/SIO3 | Reset/Hold / Quad I/O 3 | Factory-configured as HOLD# (IOC=0); configurable as RESET# via config register bit 6; disabled in SQI mode |
| SCK | Serial Clock | Timing reference for all serial transfers; sampled on rising edge for input, drives output on falling edge |
| SI/SIO0 | Serial Input / Quad I/O 0 | Default SPI input (SI); becomes bidirectional SIO0 in SQI mode after IOC=1 configuration |
Key Features
| Feature | Design Value |
|---|---|
| Quad I/O Interface (SQI) | Enables 4-bit parallel data transfer on shared SIO[3:0] lines - quadruples bandwidth vs. standard SPI at same clock rate |
| Write-Suspend Capability | Allows interruption of ongoing Program/Erase to service higher-priority reads - essential for real-time interrupt-driven firmware |
| Flexible Block Protection | Per-block write-lock (64 KByte/32 KByte/8 KByte) plus OTP lock-down - prevents accidental overwrite of bootloader or calibration data |
| JEDEC SFDP Compliance | Provides standardized, discoverable parameter table - enables automatic driver initialization in Linux/U-Boot without hard-coded timing values |
| Dual-Transfer Rate (DTR) | Sampling on both clock edges doubles effective data rate - supports high-speed firmware streaming in resource-limited SoCs |
| Security ID with Lockout | 2 KByte OTP area with factory-unique 64-bit ID and user-programmable segment - enables cryptographic key binding and anti-cloning |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Memory |
|---|---|
Use Scenario: Storing boot firmware and safety-critical configuration data in programmable logic controllers operating in harsh industrial environments. IC Role / Device Role / Timing Role: Non-volatile boot memory mapped to MCU's XIP interface; provides deterministic 104 MHz read access with <100 ns latency. Use Value: 100,000-cycle endurance and >100-year retention ensure reliable operation over 15+ year equipment lifecycles without field replacement. |
Use Scenario: Hosting boot code and sensor calibration tables for camera/radar ECUs requiring ASIL-B compliant firmware integrity. IC Role / Device Role / Timing Role: Secure, tamper-resistant firmware storage with OTP Security ID used for HMAC-based boot verification. Use Value: Factory-programmed 64-bit unique ID and lockable user-programmable segment prevent cloning and support cryptographic chain-of-trust. |
| IoT Edge Device OTA Updates | Medical Imaging System Code Storage |
Use Scenario: Enabling over-the-air firmware updates in battery-powered wireless sensors with strict power budget constraints. IC Role / Device Role / Timing Role: Low-power flash memory supporting deep power-down (2.5 µA) between update windows and fast sector erase (18 ms) for incremental patching. Use Value: Ultra-low standby current extends battery life; rapid erase/program minimizes radio-on time during update transmission. |
Use Scenario: Storing diagnostic firmware and DICOM image processing algorithms in portable ultrasound devices requiring FDA-grade reliability. IC Role / Device Role / Timing Role: High-reliability code storage with write-suspend capability - allows real-time image acquisition to preempt firmware writes without data loss. Use Value: Write-suspend ensures uninterrupted imaging sessions even during background firmware validation or logging operations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q64JWSSIQ | 64 Mbit, 1.7–2.0 V supply, 133 MHz max, 4-byte addressing default, no integrated Security ID | Lacks OTP Security ID and SQI interface; supports only standard SPI/DTR | Choose for cost-sensitive designs where cryptographic ID and quad-I/O bandwidth are not required |
| Cypress S25FL164K0XMFI011 | 64 Mbit, 2.7–3.6 V supply, 80 MHz max, HyperBus interface option, no DTR mode | Higher voltage, lower speed, different interface - incompatible with 1.8V systems and SQI-capable controllers | Choose only if migrating from legacy Cypress portfolio with existing HyperFlash layout and 3.3V rail availability |
Compared with Winbond W25Q64JWSSIQ and Cypress S25FL164K0XMFI011, the SST26WF064CT-104I/SM uniquely combines 1.8V operation, 104 MHz SQI performance, OTP Security ID, and write-suspend - making it optimal for next-generation ultra-low-power, secure, and real-time embedded systems.
Availability
SST26WF064CT-104I/SM is available at Aetrix Electronics and suitable for industrial PLCs, automotive ADAS modules, and IoT edge gateways requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for SST26WF064CT-104I/SM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog components, and memory solutions, with emphasis on reliability, longevity, and embedded system integration.
The SST26WF064CT-104I/SM belongs to Microchip's Serial Quad I/O™ flash family, designed specifically for high-performance, low-voltage firmware storage in space- and power-constrained embedded applications.
FAQ
What is the default I/O configuration of the SST26WF064CT-104I/SM at power-up?
The SST26WF064CT-104I/SM powers up with IOC = 0, enabling WP# and HOLD# functionality while disabling SIO2 and SIO3. This configures the device for standard SPI mode (x1/x2) with separate SI/SO pins. To use SQI or DTR commands, the IOC bit must be explicitly set to '1' via the Configuration Register before issuing those instructions.
Does the SST26WF064CT-104I/SM support both Mode 0 and Mode 3 SPI clock polarity/phasing?
Yes, the SST26WF064CT-104I/SM supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, SCK is low when idle; in Mode 3, SCK is high when idle. Data is always sampled on the rising edge and driven on the falling edge of SCK - consistent across both modes and compatible with common MCU SPI peripherals.
How does the Security ID feature work in the SST26WF064CT-104I/SM?
The SST26WF064CT-104I/SM includes a 2 KByte Security ID area: 64 bits are factory-programmed with a unique identifier and cannot be altered; the remainder is user-programmable. The PSID command writes to this area, and the LSID command permanently locks it. Once locked, no further writes are possible - ensuring immutable device identity for secure boot and anti-counterfeiting.
Can the SST26WF064CT-104I/SM be used in SQI mode with the WDFN-8 package?
Yes, the SST26WF064CT-104I/SM in the 8-contact WDFN package fully supports SQI mode. All four SIO pins (SIO0–SIO3) are physically present and functional. However, SQI operation requires setting IOC = 1 in the Configuration Register and using valid SQI commands (e.g., 6BH, EBH); it is disabled by default at power-up.
What happens to the Block-Protection Register after a hardware reset of the SST26WF064CT-104I/SM?
After a hardware reset, the SST26WF064CT-104I/SM restores all Block-Protection Register bits to '1' (protected), regardless of prior state. This ensures that protected blocks remain write-inhibited immediately post-reset - a safety feature preventing unintended writes during system initialization or recovery sequences.
SST26WF064CT-104I/SM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- SST26 SQI®
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 64Mbit
- Memory Organization:
- 8M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 1.5ms
- Access Time:
- -
- Voltage - Supply:
- 1.65V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIJ
SST26WF064CT-104I/SM FAQ
1.How can I place an order for SST26WF064CT-104I/SM through Aetrix?
Please submit a Request for Quotation (RFQ) for SST26WF064CT-104I/SM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SST26WF064CT-104I/SM reliable?
The price and inventory of SST26WF064CT-104I/SM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SST26WF064CT-104I/SM is usually 5 days.
3.What payment methods are accepted for SST26WF064CT-104I/SM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SST26WF064CT-104I/SM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SST26WF064CT-104I/SM?
SST26WF064CT-104I/SM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SST26WF064CT-104I/SM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SST26WF064CT-104I/SM?
For technical support, including SST26WF064CT-104I/SM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SST26WF064CT-104I/SM requirements.
6.How does Aetrix verify that SST26WF064CT-104I/SM is sourced from the original manufacturer or authorized distributors?
All SST26WF064CT-104I/SM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SST26WF064CT-104I/SM meets industry standards.
7.What is the process for return or replacement of SST26WF064CT-104I/SM?
All SST26WF064CT-104I/SM units undergo pre-shipment inspection (PSI). If there is an issue with SST26WF064CT-104I/SM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SST26WF064CT-104I/SM part is unused and in its original packaging.
Return procedure for SST26WF064CT-104I/SM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SST26WF064CT-104I/SM Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

