Microchip Technology SST26WF064CT-104I/TD
- Part No.:
- SST26WF064CT-104I/TD
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
SST26WF064CT-104I/TD.pdf
- Description:
- IC FLASH 64MBIT SPI/QUAD 24TBGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,464
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SST26WF064CT-104I/TD from Microchip Technology is a 1.8V, 64 Mbit Serial Quad I/O (SQI) flash memory IC designed for high-speed, low-power embedded boot and code storage. It delivers 104 MHz single-data-rate (SDR) clock performance, supports x1/x2/x4 SPI and SQI protocols, and features uniform 4 KByte sectors with flexible block protection - deployed in industrial-grade systems requiring reliable non-volatile storage with fast erase (18 ms sector) and program operations.
For engineers reviewing the SST26WF064CT-104I/TD datasheet, SST26WF064CT-104I/TD pinout, SST26WF064CT-104I/TD application, or SST26WF064CT-104I/TD equivalent, key selection criteria include its 1.65–1.95 V single-supply operation, 100,000-cycle endurance, 100+ year data retention, hardware reset capability, and JEDEC SFDP compliance for automated configuration discovery.
Technical Context
The SST26WF064CT-104I/TD implements a six-wire, 4-bit multiplexed I/O interface supporting both legacy SPI (Mode 0/3) and high-throughput SQI protocols, enabling quad-speed data transfer without increasing pin count. Its SuperFlash® technology uses split-gate cells and thick-oxide tunneling to achieve faster erase times and lower active current versus conventional NOR flash.
It integrates dual-transfer rate (DTR) support up to 50 MHz, burst modes (8/16/32/64-byte wrap-around), write-suspend functionality, and configurable I/O mapping via the IOC bit - allowing dynamic reassignment of WP#/HOLD#/SIO2/SIO3 pins between SPI and SQI operational modes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 64 Mbit (8 MByte) organized as uniform 4 KByte sectors and 64 KByte blocks - enables deterministic partitioning for firmware, parameter, and overlay storage. |
| Supply Voltage | 1.65–1.95 V - single low-voltage rail compatible with modern 1.8 V system power domains, eliminating level-shifting requirements. |
| Max Clock Frequency | 104 MHz SDR / 50 MHz DTR - delivers up to 416 MB/s effective throughput in x4 SQI mode, accelerating boot and code execution. |
| Endurance & Retention | 100,000 program/erase cycles minimum; >100 years data retention - validated for long-life industrial deployments without refresh. |
| Erase Time | 18 ms typical sector erase (4 KByte), 35 ms typical chip erase - reduces firmware update latency and improves OTA reliability. |
| Power Consumption | 15 mA active read current @104 MHz; 10 µA standby; 2.5 µA deep power-down - extends battery life in always-on edge devices. |
| Security Features | 2 KByte OTP Security ID (64-bit factory-unique + user-programmable); permanent lock-down for block protection bits - meets secure boot and device identity requirements. |
Pinout & Package
Package: 8-contact WDFN (6 mm × 5 mm), RoHS-compliant, industrial temperature range (−40°C to +85°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CE# | Chip Enable | Active-low enable controlling command sequence initiation; must remain low during full command/data transaction. |
| SIO[3:0] / SI/SO | Serial I/O (multiplexed) | Quad-mode data/command/address lines (SIO0–SIO3); defaults to SI/SO in SPI mode after power-up - enables protocol flexibility without PCB redesign. |
| WP# | Write Protect Input | Hardware-controlled lock for Block-Protection and Configuration registers when WPEN=1 and IOC=0 - prevents accidental firmware corruption during power transitions. |
| HOLD# / RESET# | Multi-function control pin | Configurable as HOLD# (SPI only) or RESET# (all modes); factory default = HOLD# enabled - allows pause/resume of serial transfers or full device reset without host controller intervention. |
| SCK | Serial Clock | Rising-edge sampled input timing reference; falling-edge output data strobe - defines synchronous communication timing for all SPI/SQI operations. |
| VDD / VSS | Power / Ground | 1.65–1.95 V supply and return path; decoupling required per layout guidelines to maintain signal integrity at 104 MHz. |
Key Features
| Feature | Design Value |
|---|---|
| Serial Quad I/O (SQI) Interface | Four multiplexed I/O lines delivering 4× bandwidth vs. standard SPI at same clock frequency - reduces interface latency for real-time firmware loading. |
| JEDEC SFDP Compliance | Standardized parameter table accessible via SPI read - enables automatic host driver initialization without hard-coded timing or configuration assumptions. |
| Flexible Erase Architecture | Uniform 4 KByte sectors plus dedicated 8/32/64 KByte overlay blocks - supports independent firmware, calibration, and security parameter updates without full-chip erase. |
| Write-Suspend Capability | Pause ongoing program/erase to service higher-priority reads - maintains system responsiveness during background storage operations. |
| Non-Volatile Write-Lock Lock-Down | One-time programmable (OTP) bits per protected block - permanently prevents modification of critical firmware partitions after production programming. |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Memory |
|---|---|
Use Scenario: Storing boot code and runtime firmware for programmable logic controllers operating in harsh factory environments with wide temperature swings and EMI exposure. IC Role / Device Role / Timing Role: Primary non-volatile code storage with fast random-access read and deterministic sector erase - ensures sub-100ms firmware recovery after brown-out events. Use Value: 100,000-cycle endurance and >100-year data retention guarantee field-deployed firmware integrity over 15+ year product lifecycles without maintenance. | Use Scenario: Holding safety-critical boot images and sensor calibration data for automotive camera/radar ECUs requiring ASIL-B compliant storage with tamper resistance. IC Role / Device Role / Timing Role: Secure, high-reliability boot memory interfaced via SQI to reduce MCU pin count and PCB area - supports fast cold-boot (<200 ms) and secure firmware validation. Use Value: Factory-programmed 64-bit Security ID and OTP lock-down prevent unauthorized firmware replacement and ensure traceable device identity across supply chain. |
| Medical IoT Edge Device | Smart Energy Meter Firmware |
Use Scenario: Code and configuration storage for battery-powered portable diagnostic devices requiring ultra-low standby current and secure firmware updates over BLE. IC Role / Device Role / Timing Role: Low-power persistent memory with 2.5 µA deep power-down mode - extends battery life while maintaining secure, authenticated firmware update capability. Use Value: 10 µA standby and 2.5 µA deep power-down currents enable multi-year operation on coin-cell batteries without compromising security or update speed. | Use Scenario: Storing tariff tables, metering logs, and regulatory-compliant firmware in utility-grade smart meters deployed in unattended outdoor locations. IC Role / Device Role / Timing Role: Industrial-grade flash with −40°C to +85°C operation and robust ESD tolerance - withstands thermal cycling and voltage transients common in grid infrastructure. Use Value: Uniform 4 KByte sector architecture enables atomic firmware patching and rollback, meeting ANSI C12.22 and DLMS/COSEM field upgrade requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q64JW | 64 Mbit, 1.7–1.95 V, 133 MHz SDR, no SQI support, 3.3 V tolerant I/O | Lacks SQI interface and DTR mode; requires level-shifting for 1.8 V hosts | Select when maximum clock speed is prioritized over interface flexibility and power efficiency. |
| Cypress S25FL164K | 64 Mbit, 2.7–3.6 V, 104 MHz SDR, supports XIP but no DTR or SQI | Higher voltage requirement; incompatible with 1.8 V-only systems | Choose only if existing 3.3 V design mandates pin-compatible replacement without voltage rail changes. |
Compared with W25Q64JW and S25FL164K, the SST26WF064CT-104I/TD uniquely combines 1.8 V operation, SQI/DTR support, and integrated Security ID - making it optimal for space-constrained, battery-sensitive, and security-aware embedded designs where protocol efficiency and low-voltage compatibility are mandatory.
Availability
SST26WF064CT-104I/TD is available at Aetrix Electronics and suitable for industrial automation, automotive ADAS modules, and medical IoT edge devices requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for SST26WF064CT-104I/TD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with a focus on embedded control and connectivity.
The SST26WF064CT-104I/TD belongs to Microchip's Serial Quad I/O™ (SQI™) flash family, engineered for high-performance, low-power boot and code storage in resource-constrained embedded systems demanding reliability, security, and interface efficiency.
FAQ
What is the operating voltage range for SST26WF064CT-104I/TD?
The SST26WF064CT-104I/TD operates from 1.65 V to 1.95 V - a single, tightly regulated 1.8 V supply rail. This eliminates need for external level shifters in 1.8 V systems and ensures compatibility with modern low-power MCUs. Operation outside this range may cause undefined behavior or data corruption; the device does not support 3.3 V I/O or dual-voltage operation.
Does SST26WF064CT-104I/TD support both SPI and SQI protocols?
Yes, the SST26WF064CT-104I/TD supports full backward-compatible SPI (x1/x2 modes, Mode 0/3) and high-speed SQI (x4 mode) protocols. It powers up in SPI mode by default; SQI mode is enabled via the I/O Configuration (IOC) bit and EQIO command. Pin functions dynamically remap based on protocol selection - no hardware change is needed to switch modes.
What is the purpose of the RESET#/HOLD#/SIO3 pin on SST26WF064CT-104I/TD?
The RESET#/HOLD#/SIO3 pin on SST26WF064CT-104I/TD is a multifunction terminal configurable via the RSTHLD bit in the Configuration register. By default, it operates as HOLD# in SPI mode to pause serial transfers; setting RSTHLD=1 reassigns it as a dedicated hardware RESET# pin usable in all protocols. In SQI mode, HOLD# is disabled and the pin serves as SIO3.
How does the Security ID feature work in SST26WF064CT-104I/TD?
The SST26WF064CT-104I/TD includes a 2 KByte Security ID (Sec ID) space: 64 bits factory-programmed with a unique identifier (read-only), plus user-programmable space. The PSID command writes user data; LSID locks the entire Sec ID region permanently. Once locked (SEC=1), no further writes are possible - ensuring immutable device identity and secure boot chain integrity.
Can SST26WF064CT-104I/TD be used in systems requiring JEDEC SFDP compliance?
Yes, the SST26WF064CT-104I/TD fully supports JEDEC JESD216 Serial Flash Discoverable Parameters (SFDP) standard. Its SFDP table provides host systems with standardized, versioned access to timing parameters, erase block sizes, and feature flags - enabling automatic, vendor-agnostic driver initialization without hardcoded configuration values.
SST26WF064CT-104I/TD Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- SST26 SQI®
- Package/Case:
- 24-TBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 64Mbit
- Memory Organization:
- 8M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 1.5ms
- Access Time:
- -
- Voltage - Supply:
- 1.65V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TBGA (6x8)
SST26WF064CT-104I/TD FAQ
1.How can I place an order for SST26WF064CT-104I/TD through Aetrix?
Please submit a Request for Quotation (RFQ) for SST26WF064CT-104I/TD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SST26WF064CT-104I/TD reliable?
The price and inventory of SST26WF064CT-104I/TD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SST26WF064CT-104I/TD is usually 5 days.
3.What payment methods are accepted for SST26WF064CT-104I/TD?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SST26WF064CT-104I/TD transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SST26WF064CT-104I/TD?
SST26WF064CT-104I/TD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SST26WF064CT-104I/TD order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SST26WF064CT-104I/TD?
For technical support, including SST26WF064CT-104I/TD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SST26WF064CT-104I/TD requirements.
6.How does Aetrix verify that SST26WF064CT-104I/TD is sourced from the original manufacturer or authorized distributors?
All SST26WF064CT-104I/TD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SST26WF064CT-104I/TD meets industry standards.
7.What is the process for return or replacement of SST26WF064CT-104I/TD?
All SST26WF064CT-104I/TD units undergo pre-shipment inspection (PSI). If there is an issue with SST26WF064CT-104I/TD, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SST26WF064CT-104I/TD part is unused and in its original packaging.
Return procedure for SST26WF064CT-104I/TD:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SST26WF064CT-104I/TD Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

