STMicroelectronics ST1L04PT

Overview

ST1L04PT from STMicroelectronics is an adjustable low-dropout linear voltage regulator delivering up to 1 A output current with 0.8 V minimum output voltage, ±2% reference accuracy at 25 °C, and maximum 3 mA quiescent current over 0–125 °C junction temperature. It operates with low-ESR ceramic capacitors only and integrates thermal shutdown with 5 °C hysteresis and current limiting-ideal for post-regulation in notebook PC power rails and low-voltage ASIC supplies.

For engineers reviewing the ST1L04PT datasheet, ST1L04PT pinout, ST1L04PT application, or ST1L04PT equivalent, key selection criteria include dropout voltage (1 V @ 1 A), reference voltage stability (0.776–0.824 V), load/line regulation (0.8%), ceramic capacitor compatibility (≥2.2 µF, ≤200 mΩ ESR), and thermal protection behavior under sustained 1 A load.

Technical Context

The ST1L04PT uses an internal bandgap reference (0.8 V nominal) and error amplifier to regulate output via external R1/R2 divider connected to the ADJ pin; output voltage follows VO = VREF(1 + R1/R2) + IADJR1, where IADJ is stable at ≤1 µA. Its dropout is defined as the minimum VI–VO differential required to maintain 1% regulation-1 V at 1 A for VO ≥1.8 V, overridden by minimum input voltage (2.8 V) for lower outputs.

Stability relies exclusively on low-ESR ceramic output capacitors (≥2.2 µF, ≤200 mΩ), with no requirement for tantalum or electrolytic types. Protection circuitry includes foldback current limiting and thermal shutdown triggered at 165 °C with 5 °C hysteresis, enabling safe recovery without external intervention after fault clearance.

Key Specifications

Pinout & Package

ST1L04PT is housed in a thermally enhanced PPAK (Power Package) with exposed GND pad for improved heat dissipation (Rthj-case = 8 °C/W). The package measures 6.0 × 6.4 mm with 1.27 mm pitch and is RoHS-compliant per ECOPACK® standards.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar adjustable LDO regulator applications.

Compared with TPS7A4700RGWR and ADM7150ACPZ-R7, ST1L04PT uniquely supports 0.8 V minimum output with guaranteed ceramic-capacitor-only stability and 1 A current-making it the only option among the three for cost-effective, thermally robust sub-1 V post-regulation in space-constrained embedded systems.

Availability

ST1L04PT is available at Aetrix Electronics and suitable for notebook PC power management, low-voltage ASIC supplies, and VID-based microcontroller regulation requiring stable component supply and long-lifecycle support.

Supply support for ST1L04PT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, MCU, power, and sensor solutions for industrial, automotive, and consumer markets.

The ST1L04PT belongs to ST's high-reliability linear regulator product line, engineered specifically for low-voltage, high-current post-regulation in portable computing and embedded systems where thermal efficiency and ceramic capacitor compatibility are mandatory.

FAQ

What is the minimum input voltage required for ST1L04PT to regulate 0.8 V output?

The ST1L04PT requires a minimum input voltage of 2.8 V to maintain regulation at any output voltage-including 0.8 V-due to internal circuitry headroom constraints. This is specified in Table 3 (Absolute Maximum Ratings) and confirmed in electrical characteristics under "Operating input voltage." Below 2.8 V, the device enters dropout and cannot sustain regulated output.

Can ST1L04PT be used with aluminum electrolytic output capacitors?

No-ST1L04PT is explicitly designed and characterized for stability with low-ESR ceramic capacitors only (≥2.2 µF, ≤200 mΩ). Aluminum electrolytics typically exceed 200 mΩ ESR and introduce phase lag that risks oscillation. The datasheet states "stable with low ESR ceramic capacitors only" and provides no compensation guidance for other types.

How does the ADJ pin current affect output voltage accuracy?

IADJ is specified as ≤1 µA at 25 °C and ≤200 nA change over temperature. In the output equation VO = VREF(1 + R1/R2) + IADJR1, its contribution remains below 0.5% error even with R1 = 100 kΩ. For typical R1 values ≤10 kΩ, IADJ-induced error is negligible (<0.05%) and falls within the ±2% overall accuracy budget.

Is the exposed pad on the PPAK package electrically connected?

Yes-the exposed metallic pad on the ST1L04PT PPAK package is internally connected to GND (Pin 3) and serves as both the primary thermal conduction path and a low-inductance ground return. Datasheet Table 2 confirms "The exposed metallic pad of the package is connected to GND," and mechanical drawings show it tied directly to the die substrate.