STMicroelectronics ST1L05BPUR

Overview

ST1L05BPUR from STMicroelectronics is an adjustable-output, very low quiescent current BiCMOS linear voltage regulator in DFN6 (3×3 mm) package, delivering up to 1.3 A output current with ±2% output voltage tolerance at 25 °C, 0.3 V typical dropout at 1.3 A, and integrated enable and Power Good functions. It is designed for power-sensitive data storage systems requiring stable 3.3 V supply to read channel and memory ICs.

For engineers reviewing the ST1L05BPUR datasheet, ST1L05BPUR pinout, ST1L05BPUR application, or ST1L05BPUR equivalent, key selection criteria include its ADJ-pin architecture for programmable output, thermal shutdown with hysteresis, stability with low-ESR ceramic capacitors, and dual-function EN/PG interface for system-level power sequencing and fault monitoring.

Technical Context

The ST1L05BPUR implements a BiCMOS-based error amplifier with bandgap reference and internal current-limiting circuitry, enabling precise output regulation across 0–125 °C junction temperature range. Its ADJ pin configures output via external resistor divider, while the PG pin provides open-drain status signaling when VO reaches 92% of target.

Enable logic uses internal pull-up to VI with 2 V high-threshold and 0.8 V low-threshold, supporting direct microcontroller GPIO control. The regulator maintains <650 µA quiescent current over full load (2 mA–1.3 A) and temperature range, and requires only 4.7 µF input/output ceramic capacitors for stability.

Key Specifications

Pinout & Package

ST1L05BPUR is housed in a thermally enhanced DFN6 (3×3 mm, 0.75 mm height) package with exposed thermal pad requiring PCB connection to GND for optimal thermal performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar adjustable LDO regulator applications.

Compared with TPS7A4700RGWR and ADM7172ACPZ-R7, ST1L05BPUR uniquely integrates both EN and PG in a compact DFN6 package while maintaining 1.3 A capability and BiCMOS-level quiescent current-making it optimal for space-constrained, sequenced storage power rails.

Availability

ST1L05BPUR is available at Aetrix Electronics and suitable for hard disk drives, solid-state storage controllers, industrial data acquisition systems, and embedded network attached storage requiring stable component supply with guaranteed long-term availability.

Supply support for ST1L05BPUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in power management, microcontrollers, and analog ICs for automotive, industrial, and consumer applications.

The ST1L05 series belongs to ST's high-efficiency, low-quiescent-current linear regulator product line, engineered specifically for data storage and portable electronics where thermal efficiency, small footprint, and power sequencing reliability are critical.

FAQ

What output voltage range can be set using the ADJ pin on ST1L05BPUR?

The ST1L05BPUR uses an internal 1.22 V reference connected to the ADJ pin. By configuring a resistor divider between VO and GND-with the ADJ node tied to the midpoint-the output voltage can be adjusted from 1.8 V to 5.25 V. The calculation follows VO = 1.22 × (1 + R1/R2), where R1 connects VO to ADJ and R2 connects ADJ to GND. Minimum recommended R2 is 10 kΩ to limit ADJ pin current (1 nA) and maintain accuracy.

How does the Power Good (PG) pin behave during startup and fault conditions?

The PG pin is an open-drain output that pulls low until VO reaches 92% of its final regulated value, then transitions high. During undervoltage or overtemperature shutdown, PG falls low again after a brief delay. When disabled via EN, PG remains low. It requires an external pull-up resistor (typically 10–100 kΩ to VI or system rail) and sinks up to 6 mA when asserted low. This behavior enables precise power-rail sequencing and fault reporting without external components.

Can ST1L05BPUR operate with input voltages below 3.0 V?

No. The absolute maximum rating specifies VI ≥ –0.3 V, but the minimum functional input voltage is 2.9 V per Table 9 footnote 1 ("See minimum start-up voltage, VI = 2.9 V"). Below this, the regulator cannot achieve regulation or guarantee PG assertion. For 3.3 V output applications, a minimum 3.6 V input is recommended to accommodate 0.3 V dropout and margin. Operation at 3.0 V input is only viable for outputs ≤2.7 V.

What thermal derating applies when using ST1L05BPUR in DFN6 without a thermal pad connection?

With the exposed thermal pad unconnected, R_thJA rises significantly beyond the specified 55 °C/W (Table 4). Real-world measurements show >90 °C/W in standard 2-layer PCBs without thermal vias. At 1.3 A and 5 V input, power dissipation exceeds 2.2 W-causing junction temperatures to exceed 125 °C within seconds. STMicroelectronics mandates soldering the exposed pad to a minimum 100 mm² copper pour with ≥6 thermal vias (0.3 mm diameter) to achieve rated performance and reliability.