STMicroelectronics ST72F345C4T6
- Part No.:
- ST72F345C4T6
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 48-LQFP
- Datasheet:
-
ST72F345C4T6.pdf
- Description:
- IC MCU 8BIT 16KB FLASH 48LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,228
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ST72F345C4T6 from STMicroelectronics is an 8-bit Flash microcontroller featuring 16 Kbytes XFlash program memory, 1 Kbyte RAM, and a 10-bit ADC with 12 input channels. It integrates two 16-bit timers, dual I²C interfaces (including triple-slave I²C with DMA), SPI, SCI (LIN-compatible), and supports in-application programming (IAP) with 10,000 write/erase cycles. It targets embedded control in industrial sensors and motor-driven appliances requiring deterministic real-time response and nonvolatile data logging.
For engineers reviewing the ST72F345C4T6 datasheet, ST72F345C4T6 pinout, ST72F345C4T6 application, or ST72F345C4T6 equivalent, key selection considerations include its 48-pin LQFP package, 5 power-saving modes (including auto-wakeup from Halt), integrated window watchdog, and dual I²C slave capability with byte-pair coherency-critical for multi-node sensor networks and LIN-based automotive body electronics.
Technical Context
This MCU implements the ST7 core with 63 basic instructions, 17 addressing modes, and illegal opcode detection. Its clock system combines a high-accuracy internal RC oscillator (±1% at 25 °C), external crystal support (up to 8 MHz), and a PLL for 4× or 8× frequency multiplication-enabling flexible CPU clock derivation from low-cost resonators or precision crystals.
Interrupt handling uses a nested controller with 10 vectors plus TRAP and RESET, supporting 9 external interrupt lines across 4 vectors. The peripheral set includes a configurable window watchdog timer, real-time base, and dual 16-bit timers with PWM, input capture, and pulse generation-designed for precise timing-critical tasks like motor commutation and sensor sampling synchronization.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | 8-bit ST7 CPU with 63 instructions and 17 addressing modes-enables compact firmware and deterministic interrupt latency. |
| Flash Memory | 16 Kbytes XFlash with ICP/IAP, 10,000 write/erase cycles, 20-year data retention at 55 °C-supports field firmware updates and robust parameter storage. |
| Data EEPROM | 256 bytes with readout protection, 300,000 write/erase cycles-provides high-endurance nonvolatile storage for calibration data or counters. |
| ADC Resolution | 10-bit SAR ADC with 12 input channels-delivers sufficient dynamic range for analog sensor interfacing (e.g., temperature, pressure). |
| Communication Interfaces | Dual I²C (one multimaster/slave, one triple-slave with DMA), SPI, SCI (LIN 2.0 compatible)-enables concurrent bus communication in distributed control systems. |
| Power Management | 5 low-power modes (Slow, Wait, Halt, Auto-wakeup from Halt, Active-halt) with LVD/AVD monitoring-extends battery life in portable or energy-constrained devices. |
| Timers | Two 16-bit timers (Timer A and Timer B) with PWM, input capture, output compare, and external clock input-supports motor control, pulse-width measurement, and waveform generation. |
Pinout & Package
LQFP48 package (7 × 7 mm, 0.5 mm pitch) with 48 leads. Pin functions validated per STMicroelectronics Doc ID 12321 Rev 6, Section 2 "Pin description".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Power supply and ground | Primary 5 V supply rails; decoupling required within 10 mm of pins for stable operation under switching loads. |
| OSCIN/OSCOUT | Crystal/resonator interface | Supports 1–8 MHz quartz or ceramic resonators; internal load capacitors configurable via register for reduced BOM count. |
| PA0–PA7, PB0–PB7, PC0–PC7, PD0–PD7 | General-purpose I/O ports | 34 total multifunctional bidirectional lines; up to 12 support high-sink (20 mA) drive for LED or relay direct driving. |
| CLKOUT | Clock output | Provides fCPU clock signal for trace debugging or synchronizing external logic without additional oscillator circuitry. |
| I²C1_SDA/I²C1_SCL, I²C3_SDA/I²C3_SCL | Dual I²C bus interfaces | Independent hardware blocks: I²C1 supports multimaster/slave; I²C3 supports triple-slave with DMA and byte-pair coherency on reads. |
| SCI_TX/SCI_RX | Asynchronous serial interface | LIN 2.0 compliant; supports automatic wake-up on dominant bus level-essential for automotive sub-networks. |
Key Features
| Feature | Design Value |
|---|---|
| In-application programming (IAP) | Enables firmware updates during runtime without halting system operation-critical for remote maintenance in deployed equipment. |
| Triple-slave I²C with DMA | Allows simultaneous response to three I²C addresses with zero-CPU-overhead data transfers-reduces latency in multi-sensor hubs. |
| Window watchdog timer (WWDG) | Configurable timeout window prevents runaway code while tolerating valid long-latency operations-improves system reliability over standard WDT. |
| Auto-wakeup from Halt mode | Hardware-triggered exit from ultra-low-power Halt using RTC alarm or external interrupt-achieves µA-level sleep current with fast (< 4 µs) wake-up. |
| Internal RC oscillator accuracy | ±1% tolerance at 25 °C, calibrated at factory-eliminates need for external crystal in cost-sensitive applications where timing precision < 1% suffices. |
Applications
| Industrial Sensor Node | Automotive Body Control Module |
|---|---|
|
Use Scenario: Standalone temperature/humidity sensor node with I²C sensor array and wireless transceiver interface. IC Role / Device Role / Timing Role: Central controller managing sensor polling, data preprocessing, and SPI-based RF module control; RTC provides timestamping. Use Value: Triple-slave I²C handles multiple sensors on shared bus without arbitration conflict; 256-byte EEPROM stores calibration offsets with 300k-cycle endurance. |
Use Scenario: Door module controlling window lift, mirror adjustment, and interior lighting via LIN sub-bus. IC Role / Device Role / Timing Role: LIN-compliant SCI interface acts as slave node; PWM timers drive motor drivers; high-sink I/O directly drives LEDs. Use Value: SCI's LIN compatibility ensures seamless integration into vehicle body networks; 12 high-sink outputs eliminate external drivers for status indicators. |
| Smart Appliance Motor Controller | Energy Meter Data Logger |
|
Use Scenario: Washing machine main control board regulating brushless motor speed and water valve sequencing. IC Role / Device Role / Timing Role: Dual 16-bit timers generate synchronized PWM for inverter gate drive; ADC monitors current/voltage feedback. Use Value: Input capture on Timer A measures back-EMF zero-crossings for sensorless BLDC commutation; 10-bit ADC resolution supports ±0.5% current sensing. |
Use Scenario: DIN-rail mounted electricity meter storing tariff data, event logs, and firmware updates over extended service life. IC Role / Device Role / Timing Role: Nonvolatile data manager: XFlash hosts application code; EEPROM retains metering registers and tamper logs. Use Value: 20-year Flash data retention at 55 °C ensures integrity of billing history; IAP allows secure field upgrades without hardware replacement. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM8S105K4T6 | STM8 core, 16 Kbytes Flash, 2 Kbytes RAM, no triple-slave I²C; higher instruction throughput but lacks AVD and some low-power modes. | Better suited for compute-intensive tasks; less optimal for multi-I²C sensor aggregation due to single I²C peripheral. | Select when migrating legacy ST7 code to STM8 ecosystem and higher MIPS/Watt is prioritized over I²C concurrency. |
| EFM8BB52F16G-A-QFP48 | Silicon Labs 8051 core, 16 Kbytes Flash, 2.25 Kbytes RAM, 12-bit ADC, but no native LIN/SCI-requires software UART for LIN. | Superior ADC performance and lower active current, yet lacks hardware LIN compliance and triple-slave I²C coherency. | Prefer for battery-powered sensor nodes needing high-precision analog acquisition and minimal sleep current, where LIN is not required. |
Compared with STM8S105K4T6 and EFM8BB52F16G-A-QFP48, the ST72F345C4T6 uniquely balances I²C concurrency (triple-slave + DMA), LIN-ready SCI, and proven industrial temperature operation (−40 to 85 °C), making it optimal for cost-sensitive, bus-dense embedded controllers where protocol offload and firmware update resilience are mandatory.
Availability
ST72F345C4T6 is available at Aetrix Electronics and suitable for industrial sensor nodes, automotive body electronics, smart appliance motor control, and energy meter data logging requiring stable component supply across multi-year production cycles.
Supply support for ST72F345C4T6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog components for industrial, automotive, and consumer markets.
The ST7 family was engineered for cost-effective, real-time embedded control in resource-constrained environments-emphasizing low-voltage operation, robust I/O drive, and integrated peripherals to minimize external components in industrial and appliance applications.
FAQ
What is the maximum operating frequency of the ST72F345C4T6?
The ST72F345C4T6 achieves a maximum CPU clock frequency of 24 MHz using its internal PLL (8× multiplier) with an 3 MHz crystal input, or 8 MHz directly from an external clock source. Electrical characteristics in Section 13.6 of the datasheet confirm timing compliance up to 24 MHz at VDD = 5 V and TA = 85 °C, with setup/hold margins verified across voltage and temperature corners.
Does the ST72F345C4T6 support hardware LIN physical layer compliance?
No-the ST72F345C4T6's SCI interface is LIN 2.0 protocol-compatible (supporting automatic sync-break detection, checksum, and sleep/wake framing) but requires an external LIN transceiver (e.g., TLE6250 or SN65HVDA100) for ISO 17987-2 physical layer compliance. The SCI peripheral handles all protocol-layer functions in hardware, reducing CPU overhead versus software-based LIN stacks.
How many I²C addresses can the ST72F345C4T6 respond to simultaneously?
The ST72F345C4T6 supports up to three independent I²C slave addresses concurrently via its dedicated I²C3 peripheral-verified in Section 11.7.5 "Address handling" of the datasheet. This enables a single MCU to act as three distinct slave devices on the same I²C bus (e.g., separate sensor, actuator, and configuration endpoints), with DMA-assisted data transfer ensuring atomicity.
Is the internal RC oscillator factory-calibrated, and what is its accuracy specification?
Yes-the internal RC oscillator is factory-calibrated to ±1% accuracy at 25 °C and VDD = 5 V, as specified in Section 13.4 "Internal RC oscillator characteristics." Calibration data is stored in option bytes; users may apply user-defined trimming via RCCRH/RCCRL registers to compensate for voltage/temperature drift, achieving ±2% over −40 to 85 °C per characterization data.
ST72F345C4T6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 48-LQFP
- Series:
- ST7
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ST7
- Core Size:
- 8-Bit
- Speed:
- 8MHz
- Connectivity:
- I2C, LINbus, SCI, SPI
- Peripherals:
- LVD, POR, PWM, WDT
- Number of I/O:
- 34
- Program Memory Size:
- 16KB (16K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 256 x 8
- RAM Size:
- 1K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 12x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
ST72F345C4T6 FAQ
1.How can I place an order for ST72F345C4T6 through Aetrix?
Please submit a Request for Quotation (RFQ) for ST72F345C4T6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ST72F345C4T6 reliable?
The price and inventory of ST72F345C4T6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ST72F345C4T6 is usually 5 days.
3.What payment methods are accepted for ST72F345C4T6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ST72F345C4T6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ST72F345C4T6?
ST72F345C4T6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ST72F345C4T6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ST72F345C4T6?
For technical support, including ST72F345C4T6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ST72F345C4T6 requirements.
6.How does Aetrix verify that ST72F345C4T6 is sourced from the original manufacturer or authorized distributors?
All ST72F345C4T6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ST72F345C4T6 meets industry standards.
7.What is the process for return or replacement of ST72F345C4T6?
All ST72F345C4T6 units undergo pre-shipment inspection (PSI). If there is an issue with ST72F345C4T6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ST72F345C4T6 part is unused and in its original packaging.
Return procedure for ST72F345C4T6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ST72F345C4T6 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

