My Inquiry
My Account
STMicroelectronics ST72F623F2M1TR
- Part No.:
- ST72F623F2M1TR
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
ST72F623F2M1TR.pdf
- Description:
- IC MCU 8BIT 8KB FLASH 20SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:4,720
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ST72F623F2M1TR from STMicroelectronics is an 8-bit USB-enabled microcontroller with dual-voltage Flash (8 KB), 384 bytes RAM, integrated USB 2.0 low-speed interface (3 endpoints), 10-bit ADC (8 channels), and two 8-bit timers (ART + TBU). It operates from 4.0–5.5 V, supports three power-saving modes, and targets embedded USB peripheral control in industrial and consumer devices.
For engineers reviewing the ST72F623F2M1TR datasheet, ST72F623F2M1TR pinout, ST72F623F2M1TR application, or ST72F623F2M1TR equivalent, key selection criteria include USB transceiver integration, Flash programmability, analog input count, interrupt vector depth, and LQFP44 package compatibility with PCB layout constraints for USB signal integrity.
Technical Context
This MCU implements a proprietary 8-bit ST7 core with nested interrupts, true bit manipulation, and 8×8 unsigned multiply. Its USB subsystem includes on-die 3.3 V regulator, differential transceivers (USBDP/USBDM), suspend/resume logic, and DMA support-enabling self-powered or bus-powered low-speed USB device operation without external PHY.
The peripheral set is tightly coupled: ART timer provides PWM outputs and input capture synchronized to USB frame timing; 10-bit ADC supports up to 8 analog inputs with configurable sampling triggers; SCI and SPI interfaces share port resources and support simultaneous use with USB under software-managed priority.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | 8-bit ST7 CPU with 63 instructions, 17 addressing modes, and nested interrupt handling up to 12 vectors |
| Program Memory | 8 KB dual-voltage Flash (1.8–5.5 V write), supporting In-Application Programming (IAP) and read-write protection |
| RAM | 384 bytes total, including 128-byte hardware stack (0100h–017Fh), zero-page addressing support |
| USB Interface | Low-speed (1.5 Mbps) USB 2.0 compliant with integrated 3.3 V regulator, transceivers, and 3 endpoints (control + 2 bulk/interrupt) |
| Analog-to-Digital Converter | 10-bit successive approximation ADC with 8 input channels (PA0–PA7), programmable sampling time, and conversion trigger via timer or software |
| Timers | 8-bit Auto-Reload Timer (ART) with 2 PWM outputs, 2 input captures, and external clock input; plus Time Base Unit (TBU) for periodic interrupts |
| Supply Voltage | 4.0–5.5 V digital supply (VDD/VSS); separate analog supply (VDDA/VSSA) and USB 3.3 V output (USBVCC) |
| Operating Temperature | 0°C to +70°C ambient, validated per JEDEC JESD22-A104 for industrial-grade reliability |
Pinout & Package
LQFP44 package (10 × 10 mm, 0.8 mm pitch) with exposed thermal pad; pin-compatible with ST7262xxx family variants. Pin 39 is reserved and must remain unconnected.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD / VSS | Digital power supply and ground | Decoupling required at each VDD pin; VSS must connect to VSSA and USB ground plane for noise immunity |
| USBDP / USBDM | USB differential data pair | Impedance-controlled 90 Ω differential routing required; 1.5 kΩ pull-up on USBDP enables USB enumeration as full-speed-capable device |
| USBVCC | On-chip 3.3 V regulator output | Supplies internal USB transceivers; requires 10 µF ceramic capacitor to VSS for stability |
| PA0–PA7 | Analog input / interrupt / USB control | PA0 doubles as USBOE (USB Output Enable); all pins support analog input, interrupt edge detection, and digital I/O |
| PB0–PB7 | High-sink I/O with timer/SCI/USB functions | HS-rated (8 mA @ 0.4 V) for driving LEDs or optocouplers; PB3–PB5 serve ART clock/capture; PB6/PB7 are PWM outputs |
| PC0–PC7 | SPI/SCI multiplexed I/O | PC3–PC6 implement full SPI master/slave (SCK/MOSI/MISO/SS); PC2–PC5 also serve as external interrupt sources (IT9–IT12) |
| PD0–PD6 | General-purpose I/O | 7-bit port with no alternate functions; supports weak pull-ups, floating input, and interrupt capability on PD0/PD1 |
| RESET | Active-low non-maskable reset | Internal POR and LVD generate reset; external reset pulse must exceed 2.5 µs minimum width |
Key Features
| Feature | Design Value |
|---|---|
| In-Application Programming (IAP) | Enables firmware updates over USB or SCI without external programmer; preserves EEPROM-like data during Flash rewrites |
| Integrated USB Transceiver | Eliminates need for external PHY or level-shifting components; reduces BOM cost and PCB area by >30% vs discrete solutions |
| Low-Voltage Detector (LVD) | Monitors VDD and asserts reset at 3.8 V (±0.15 V) to prevent erratic operation during brown-out conditions |
| Three Power-Saving Modes | WAIT (CPU halted, peripherals active), SLOW (reduced clock), HALT (all clocks stopped except LVD/RTC)-achieving <1 µA standby current |
| Hardware Watchdog Timer | Configurable timeout from 8 ms to 500 ms; independent RC oscillator ensures reliable recovery even if main clock fails |
| True Bit Manipulation | Direct SET/CLR/TEST instructions on any bit address reduce firmware size and improve real-time response vs software emulation |
Applications
| USB Human Interface Device (HID) | Industrial Sensor Node |
|---|---|
|
Use Scenario: USB keyboard, mouse, or custom HID peripheral with local button/LED control and analog sensor feedback. IC Role / Device Role / Timing Role: Primary USB device controller managing HID report descriptors, endpoint buffering, and host polling responses. Use Value: Integrated USB transceiver and 8 KB Flash enable single-chip HID implementation without external PHY or boot ROM, reducing system latency and component count. |
Use Scenario: Remote temperature/humidity monitor with analog sensor inputs, local display, and USB data upload to host PC. IC Role / Device Role / Timing Role: Data acquisition hub performing 10-bit ADC sampling, timestamping via ART timer, and USB bulk transfers of calibrated readings. Use Value: Simultaneous ADC conversion triggering and USB DMA transfer minimize CPU overhead, enabling 100+ samples/sec throughput with <5% CPU utilization. |
| USB Firmware Updater | Embedded USB-to-Serial Bridge |
|
Use Scenario: Field-upgradable embedded module where new firmware is delivered via USB mass storage or vendor-specific class. IC Role / Device Role / Timing Role: Secure bootloader executing IAP routines while validating signature and CRC of incoming firmware images. Use Value: Dual-voltage Flash allows safe erase/write under 3.3 V USB power; memory protection prevents accidental overwrite of critical bootloader section. |
Use Scenario: USB-to-RS232/RS485 converter for legacy industrial equipment interfacing with modern PCs. IC Role / Device Role / Timing Role: Protocol translator mapping USB CDC ACM class requests to SCI UART framing with baud rate generation via ART timer. Use Value: Hardware SCI with automatic break detection and framing error handling offloads timing-critical UART tasks from host CPU, ensuring reliable 115.2 kbps operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar USB-enabled microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM8S105K4T6C | 16 MHz STM8 core, 16 KB Flash, no integrated USB transceiver (requires external PHY), higher ADC resolution (10-bit with differential mode) | Requires external USB PHY and level shifters; better suited for high-precision analog systems needing >8 ADC channels | Select when higher clock speed, larger Flash, or differential ADC inputs are required-and board space allows external USB components. |
| ATMEGA32U4-AU | AVR core, 32 KB Flash, native USB 2.0 full-speed (12 Mbps), built-in PLL, no dedicated LVD or hardware watchdog | Supports full-speed USB HID/CDC classes out-of-box; lacks integrated voltage monitoring and robust brown-out reset behavior | Choose for full-speed USB applications requiring higher bandwidth or mature LUFA/Arduino ecosystem support, accepting trade-offs in power monitoring rigor. |
Compared with STM8S105K4T6C and ATMEGA32U4-AU, the ST72F623F2M1TR offers lower system-level BOM cost due to integrated USB transceiver and LVD, tighter real-time control via nested interrupts, and proven industrial temperature stability-but at the expense of USB speed and Flash capacity.
Availability
ST72F623F2M1TR is available at Aetrix Electronics and suitable for USB peripheral control, industrial sensor nodes, and embedded firmware updater modules requiring stable component supply across extended production lifecycles.
Supply support for ST72F623F2M1TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors since 1987.
The ST7 microcontroller family was engineered specifically for cost-sensitive, USB-connected embedded applications requiring low-power operation, Flash flexibility, and analog integration-targeting industrial controls, PC peripherals, and smart consumer devices.
FAQ
What USB speed and device class does ST72F623F2M1TR support?
The ST72F623F2M1TR implements USB 2.0 low-speed (1.5 Mbps) compliance with integrated transceivers and supports standard device classes including HID, CDC ACM, and vendor-defined protocols. It does not support full-speed (12 Mbps) or high-speed USB modes. Endpoint configuration is fixed at one control endpoint and two additional endpoints (bulk or interrupt), managed entirely in firmware using the provided USB SIE registers.
Can ST72F623F2M1TR operate from a 3.3 V supply?
No-the ST72F623F2M1TR requires a 4.0–5.5 V digital supply (VDD) for proper Flash programming and core operation. While its USBVCC pin delivers a regulated 3.3 V for internal transceivers, the main VDD must be ≥4.0 V. ROM variants (e.g., ST72623F2) support 3.0–5.5 V, but this Flash-based part does not. Operating below 4.0 V risks Flash corruption and undefined reset behavior.
How is the 10-bit ADC triggered and what is its maximum sampling rate?
The 10-bit ADC supports software start, ART timer overflow, or TBU interrupt as conversion triggers. Maximum sampling rate is 100 kSPS under optimal conditions (VDD = 5 V, ADCCLK = 8 MHz, 10-bit resolution, no wait states). Conversion time is 13 ADCCLK cycles (1.625 µs at 8 MHz), and the result is stored in a 16-bit register with left-justified 10-bit data. External analog inputs must be ≤VDDA and ≥VSSA, with recommended source impedance <10 kΩ.
Is ST72F623F2M1TR pin-compatible with other ST7262xxx variants?
Yes-within the same package variant. The ST72F623F2M1TR in LQFP44 is pin-compatible with ST72F622L2, ST72F621K4, and ST72621J4 in the same LQFP44 footprint. Differences lie in Flash/RAM size, peripheral enablement (e.g., SPI presence), and factory-programmed option bytes-not pin function or electrical characteristics. Pin 39 remains reserved across all LQFP44 versions and must be left unconnected.
ST72F623F2M1TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Series:
- ST7
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ST7
- Core Size:
- 8-Bit
- Speed:
- 8MHz
- Connectivity:
- USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 11
- Program Memory Size:
- 8KB (8K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 384 x 8
- Voltage - Supply (Vcc/Vdd):
- 4V ~ 5.5V
- Data Converters:
- A/D 3x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
ST72F623F2M1TR FAQ
1.How can I place an order for ST72F623F2M1TR through Aetrix?
Please submit a Request for Quotation (RFQ) for ST72F623F2M1TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ST72F623F2M1TR reliable?
The price and inventory of ST72F623F2M1TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ST72F623F2M1TR is usually 5 days.
3.What payment methods are accepted for ST72F623F2M1TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ST72F623F2M1TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ST72F623F2M1TR?
ST72F623F2M1TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ST72F623F2M1TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ST72F623F2M1TR?
For technical support, including ST72F623F2M1TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ST72F623F2M1TR requirements.
6.How does Aetrix verify that ST72F623F2M1TR is sourced from the original manufacturer or authorized distributors?
All ST72F623F2M1TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ST72F623F2M1TR meets industry standards.
7.What is the process for return or replacement of ST72F623F2M1TR?
All ST72F623F2M1TR units undergo pre-shipment inspection (PSI). If there is an issue with ST72F623F2M1TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ST72F623F2M1TR part is unused and in its original packaging.
Return procedure for ST72F623F2M1TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ST72F623F2M1TR Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
