STMicroelectronics STBC15QTR

Overview

STBC15QTR from STMicroelectronics is a linear battery charger IC optimized for thin-film batteries, implementing CC-CV charging with 40 mA max current, 4.2 V floating voltage (±0.5%), and 250 nA battery leakage current. It integrates over-discharge protection with shelf-mode activation (≤10 nA), reverse current blocking, and open-drain PG/CHGINOK status outputs - deployed in ultra-low-power IoT wearables and energy-harvesting sensor nodes.

For engineers reviewing the STBC15QTR datasheet, STBC15QTR pinout, STBC15QTR application, or STBC15QTR equivalent, key selection criteria include programmable charge current (8–40 mA via ISET pins), selectable float voltage (4.00–4.20 V via VSET pins), peak mode threshold adjustment (PKM), and dual-package availability (QFN12 1.7×2.0 mm / Flip-chip12 1.1×1.4 mm).

Technical Context

The STBC15QTR implements a dedicated finite-state machine for CC/CV charging without pre-charge or termination phases, targeting low-capacity thin-film cells. Its internal M3 transistor provides battery disconnection during over-discharge (VBAT_OVD = 3.25 V nominal), while the PKM pin lowers that threshold to 2.25 V for transient load support.

Shelf-mode is activated by a high-level signal on SM (internal 100 kΩ pull-down), reducing quiescent current to ≤10 nA; reverse current protection is enforced by automatic M1 gate control when CHGIN falls below UVLO (3.5 V). All configuration pins (VSET0/1, ISET0/1) are logic-level digital inputs with no internal pull resistors and require hard tie to CHGIN or GND.

Key Specifications

Pinout & Package

STBC15QTR is supplied in QFN12 (1.7 × 2.0 mm, 0.55 mm max height, 400 µm pitch) with wettable flanks per ECOPACK® specifications. Pin mapping is validated per DS12551 Rev 2 Figure 2 and Table 2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar linear thin-film battery charging applications.

Compared with STBC15LJTR, STBC15QTR offers thinner-film-specific voltage ranges and PKM-adaptive over-discharge, while BQ25504RGTT enables sub-1 V harvesting but adds board area and complexity - making STBC15QTR optimal for space-constrained, 3–5 V source, thin-film applications.

Availability

STBC15QTR is available at Aetrix Electronics and suitable for fitness wearables, energy-harvesting sensors, and portable health care devices requiring stable component supply across extended production lifecycles.

Supply support for STBC15QTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in power management, microcontrollers, and analog ICs for industrial, automotive, and consumer markets.

The STBC15 product line delivers ultra-low-quiescent linear chargers specifically engineered for emerging thin-film and printed battery technologies in maintenance-free IoT edge nodes.

FAQ

What is the minimum input voltage required for STBC15QTR to initiate charging?

The STBC15QTR begins charging when CHGIN exceeds its undervoltage lockout rising threshold of 3.5 V (typical), verified across −40°C to +85°C. Below this, the device remains in standby with ≤1000 nA supply current and disables M1/M3 switches to prevent reverse current or partial charging.

How does the PKM pin affect over-discharge protection behavior?

When PKM is pulled low, the STBC15QTR reduces its battery over-discharge disconnection threshold from 3.25 V (nominal) to 2.25 V (nominal), allowing temporary operation below normal cutoff during high-pulse loads like RF transmission - without triggering permanent disconnect or FF retention.

Can VSET0 and VSET1 be left floating, or must they be tied to CHGIN or GND?

VSET0 and VSET1 must be hard-tied to either CHGIN or GND - the device has no internal pull resistors. Floating these pins causes undefined floating voltage selection and may result in unstable CV regulation or failure to enter correct charging state per Table 6.

What is the purpose of the CHGINOK open-drain output, and how should it be interfaced?

CHGINOK signals input source validity: it goes high-impedance when CHGIN ≥ 3.5 V and pulls low otherwise. It is logic-negated, so external pull-up to OUT (or system rail) is required; the output sinks ≤1 mA and leaks ≤0.2 µA when high-z - enabling direct MCU GPIO monitoring without level shifters.