STMicroelectronics STEF05SGR
- Part No.:
- STEF05SGR
- Manufacturer:
- STMicroelectronics
- Category:
- Current Regulation/Management
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
STEF05SGR.pdf
- Description:
- IC ELECTRONIC FUSE 10DFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,313
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Product details
Overview
STEF05SGR from STMicroelectronics is a latch-type integrated electronic fuse designed for 5 V DC power rail protection in hot-swap and storage applications. It features 40 mΩ RDS(on), 5.7 V typical output overvoltage clamp, adjustable current limit (2–5.2 A via RLIM), thermal shutdown at 165 °C, and programmable soft-start slew rate. It operates across 3.5–5.5 V input and delivers up to 3.5 A continuous current at 25 °C.
For engineers reviewing the STEF05SGR datasheet, STEF05SGR pinout, STEF05SGR application, or STEF05SGR equivalent, this device serves as a precision series protection switch with configurable fault response, critical for SSD/HDD power sequencing, hot-plug board enablement, and 5 V rail integrity assurance in data-center and industrial embedded systems.
Technical Context
The STEF05SGR integrates an N-channel power MOSFET with internal current-sense FET ratio, enabling accurate overload detection and foldback current limiting based on external RLIM. Its UVLO (2.9 V turn-on, 0.15 V hysteresis) prevents operation below safe rail voltage, while its dV/dt control circuit-using internal or external capacitance-governs output ramp time from 10% to 90% of VOUT (1.35 ms base, scalable to 31.5 ms).
Thermal protection triggers at 165 °C junction temperature, forcing latch-off and pulling the En/Fault pin to ~1.3 V to signal fault condition; reset requires either VCC cycling or En/Fault pin pulldown below 0.5 V. The TSOT23-8L package provides 140 °C/W junction-to-ambient thermal resistance on a 4-layer PCB, with power dissipation limited by ambient temperature and layout copper area.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCLAMP | 5.7 V typical - clamps output during input overvoltage (e.g., 8 V rail), preventing downstream IC damage |
| RDS(on) | 40 mΩ at TJ = 25 °C - minimizes voltage drop (<200 mV @ 5 A) and power loss in normal operation |
| ILIM Range | 3.2–5.2 A (RLIM = 49.9–22 Ω) - user-configurable overload threshold before foldback limiting activates |
| Soft-start Time | 1.35 ms (no Cdv/dt) to 31.5 ms (1 nF) - controls inrush current during hot-swap or capacitive load startup |
| TSHDN | 165 °C ±5 °C - thermal cutoff point; hysteresis ensures safe restart only after die cools to ~145 °C |
| UVLO Threshold | 2.9 V rising, 2.75 V falling - prevents erratic behavior during brown-out or weak 5 V supply conditions |
| En/Fault Logic | Tri-state interface: floating = enabled; <0.5 V = disabled; ~1.3 V = thermal fault latched - enables system-level monitoring and coordinated shutdown |
Pinout & Package
STEF05SGR is housed in a thermally enhanced TSOT23-8L package (2.9 × 2.8 × 0.9 mm), with exposed source pads (pins 5–6) and dual VCC inputs (pins 7–8) for low-inductance power delivery. Thermal performance relies on PCB copper area under the package leads.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (ILim) | Current limit reference | Connects to external RLIM to set ILIM/ISHORT; open/short causes failure - trace must be short and low-parasitic |
| 2 (En/Fault) | Enable/fault status bidirectional node | Float = ON; pulled low = OFF; ~1.3 V = thermal latch fault - supports daisy-chained fault signaling |
| 3 (dV/dt) | Soft-start timing control | Internal 1.35 ms ramp; add capacitor to extend ramp time linearly (Δt ≈ 1.35 + 0.03×CpF ms) |
| 4 (GND) | Reference ground | Return path for bias, sensing, and thermal feedback - must be low-impedance and adjacent to power GND planes |
| 5–6 (Source/VOUT) | Output power terminal | Drives load; also connects to internal MOSFET source - high-current path requiring wide copper traces |
| 7–8 (VCC) | Input power supply | Dual pins reduce IR drop and inductance; connect directly to input capacitor (≥1 µF ceramic, near device) |
Key Features
| Feature | Design Value |
|---|---|
| Adjustable current limit | Configured via single external resistor (RLIM); supports 2–5.2 A overload thresholds without redesign |
| Programmable soft-start | Output voltage slew rate controlled by optional external capacitor on dV/dt pin - eliminates inrush-induced bus droop |
| Overvoltage clamp | Regulates output to ≤5.9 V (max) during input overvoltage - protects 5 V logic and memory interfaces without external TVS |
| Latch-off thermal protection | Permanently disables output at 165 °C and asserts fault signal until manual reset - prevents uncontrolled re-enabling in overheated systems |
| Integrated 40 mΩ MOSFET | Eliminates discrete FET + driver + sense + protection IC complexity - reduces BOM count and layout area in space-constrained SSD modules |
Applications
| Hard Disk / SSD Power Sequencing | Hot-Swap Board Enablement |
|---|---|
|
Use Scenario: Controlled power-up of SATA/NVMe SSDs during live insertion into backplane slots. IC Role / Device Role / Timing Role: Series eFuse providing inrush-limited 5 V rail delivery, UVLO hold-off, and overcurrent isolation during plug-in transients. Use Value: Prevents backplane voltage sag and upstream supply overload; enables reliable enumeration without host reset. |
Use Scenario: Safe insertion of PCIe expansion cards or modular compute blades into powered chassis. IC Role / Device Role / Timing Role: Primary 5 V rail protector with programmable soft-start and latch-off fault response. Use Value: Eliminates arcing and contact bounce damage; guarantees clean power ramp and deterministic fault isolation per slot. |
| RAID Controller Board Protection | Industrial Embedded 5 V Distribution |
|
Use Scenario: Redundant 5 V supply management across multiple drive bays in enterprise RAID enclosures. IC Role / Device Role / Timing Role: Per-bay eFuse with En/Fault pin daisy-chaining to trigger simultaneous shutdown during thermal event. Use Value: Enables system-level thermal coordination without MCU intervention - improves MTBF and serviceability. |
Use Scenario: Power distribution to FPGA I/O banks, microcontroller peripherals, and sensor interfaces in factory automation controllers. IC Role / Device Role / Timing Role: Fault-isolating series switch with precise current limit and overvoltage clamp for mixed-voltage subsystems. Use Value: Replaces mechanical fuses and discrete protection circuits - achieves faster response, no wear-out, and diagnostic visibility. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar electronic fuse applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS25982L (Texas Instruments) | Auto-retry thermal response; 3.5–20 V input; 4.5 mΩ RDS(on); ILIM set digitally via I2C | Requires MCU interface and firmware support; better suited for systems needing automatic recovery | Select when thermal events are transient and autonomous recovery is preferred over latched safety shutdown |
| AP22653WU (Diodes Inc.) | Latch-off version; 4.5–36 V input; 60 mΩ RDS(on); fixed 5.5 V clamp; no dV/dt adjustment | Simpler layout (no RLIM/Cdv/dt), but lacks programmable current limit and soft-start tuning | Select for cost-sensitive 5 V applications where fixed protection thresholds and minimal external components are prioritized |
Compared with TPS25982L and AP22653WU, STEF05SGR offers unique balance of analog configurability (RLIM-based current limit, capacitor-tuned soft-start) and deterministic latch-off behavior - ideal for mission-critical 5 V storage and hot-swap systems where manual reset ensures verified fault clearance before reactivation.
Availability
STEF05SGR is available at Aetrix Electronics and suitable for hard disk drives, SSD modules, and hot-swap board designs requiring stable component supply, long-term lifecycle continuity, and automotive-grade reliability validation.
Supply support for STEF05SGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in power management, analog, and microcontroller solutions for industrial, automotive, and consumer markets.
The STEF series targets high-reliability DC power rail protection, with the STEF05SGR specifically engineered for precise 5 V system safeguarding in data storage and modular computing infrastructure.
FAQ
What is the function of the ILim pin, and what happens if it's left unconnected?
The ILim pin sets the current limit threshold via an external resistor (RLIM) between ILim and Source/VOUT. If left unconnected (open), the current limit circuit fails to activate, resulting in uncontrolled overcurrent response and potential device destruction during fault conditions. STMicroelectronics explicitly warns that missing or shorted RLIM may cause permanent damage.
How does the En/Fault pin behave during thermal shutdown on STEF05SGR?
During thermal shutdown, the En/Fault pin transitions from high (~5 V) to a stable intermediate voltage of 1.2–1.45 V (typ. 1.3 V), signaling latch-off fault to external monitoring circuitry. This state persists until manually reset by pulling En/Fault below 0.5 V and releasing, or by cycling VCC. It does not auto-recover.
Can STEF05SGR protect against reverse current flow from output to input?
No - STEF05SGR contains an intrinsic body diode that conducts reverse current if VOUT > VIN, risking damage during fast input dips or back-driving scenarios. ST recommends adding an external Schottky diode in anti-parallel configuration across the eFuse or a series diode in the power path to block reverse conduction.
What is the minimum recommended input/output capacitance, and why is placement critical?
Minimum 1 µF ceramic capacitor is required on both input (CIN) and output (COUT). These must be placed as close as possible to their respective pins to suppress inductive voltage spikes generated during current interruption. Poor placement increases risk of input overshoot (>25 V absolute max) or output undershoot, potentially damaging the device or downstream loads.
STEF05SGR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Electronic Fuse
- Sensing Method:
- -
- Accuracy:
- -
- Voltage - Input:
- 10V
- Current - Output:
- 3.6A
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
STEF05SGR FAQ
1.How can I place an order for STEF05SGR through Aetrix?
Please submit a Request for Quotation (RFQ) for STEF05SGR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STEF05SGR reliable?
The price and inventory of STEF05SGR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STEF05SGR is usually 5 days.
3.What payment methods are accepted for STEF05SGR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STEF05SGR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STEF05SGR?
STEF05SGR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STEF05SGR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STEF05SGR?
For technical support, including STEF05SGR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STEF05SGR requirements.
6.How does Aetrix verify that STEF05SGR is sourced from the original manufacturer or authorized distributors?
All STEF05SGR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STEF05SGR meets industry standards.
7.What is the process for return or replacement of STEF05SGR?
All STEF05SGR units undergo pre-shipment inspection (PSI). If there is an issue with STEF05SGR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STEF05SGR part is unused and in its original packaging.
Return procedure for STEF05SGR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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