STMicroelectronics STGAP2DM

Overview

STGAP2DM from STMicroelectronics is a galvanically isolated dual-channel 4 A half-bridge gate driver IC for high-voltage power stages, featuring 1700 V input-to-output isolation, ±100 V/ns CMTI, 75 ns max propagation delay, and integrated UVLO, thermal shutdown, and configurable interlocking. It drives IGBTs or SiC MOSFETs in industrial motor inverters up to 1200 V.

For engineers reviewing the STGAP2DM datasheet, STGAP2DM pinout, STGAP2DM application, or STGAP2DM equivalent, key selection criteria include isolated dual-channel timing accuracy, rail-to-rail 4 A sink/source drive capability, VH supply UVLO thresholds (9.1 V turn-on), interlocking enable/disable via iLOCK pin, and SO-16 package compatibility with high-voltage PCB creepage requirements.

Technical Context

The STGAP2DM implements two independent isolated gate driving channels with separate floating supplies (VH_A/VH_B) and grounds (GNDISO_A/GNDISO_B), enabling unipolar or bipolar gate driving configurations. Its internal level shifters and UVLO comparators operate independently per channel, supporting asymmetric topologies like three-phase inverters with split DC-link sensing.

Control logic resides on the low-voltage side (VDD/GND), while output buffers are fully isolated and rated for 1700 V transient isolation voltage. The iLOCK pin provides hardware-selectable interlocking-tied to VDD for shoot-through prevention or GND for parallel channel operation-without software intervention.

Key Specifications

Pinout & Package

STGAP2DM is housed in a SO-16 narrow-body package (9.8 × 3.9 mm, 1.27 mm pitch) with reinforced insulation and 4 mm minimum creepage/clearance between primary and secondary sides.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel isolated gate driver applications.

Compared with Si8239AD-IS and UCC5390SCD, STGAP2DM uniquely combines 4 A drive, configurable interlocking, dedicated BRAKE, and sub-100 µA standby - making it optimal for industrial inverters requiring functional safety, energy efficiency, and deterministic fault response.

Availability

STGAP2DM is available at Aetrix Electronics and suitable for industrial motor drives, UPS systems, and battery charging equipment requiring stable component supply, long-term lifecycle support, and UL-recognized isolation compliance.

Supply support for STGAP2DM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog components for industrial, automotive, and consumer markets.

STGAP2DM belongs to ST's STGAP family of isolated gate drivers, engineered specifically for high-reliability industrial inverters where galvanic isolation, shoot-through immunity, and robust fault handling are non-negotiable design requirements.

FAQ

What is the maximum allowable differential voltage between GNDISO_A and GNDISO_B?

The STGAP2DM supports ±1500 V DC or peak differential voltage between GNDISO_A and GNDISO_B, as specified in the recommended operating conditions. This enables use in split-bus or multi-level inverter topologies where isolated half-bridges operate at different common-mode potentials, provided PCB layout maintains ≥4 mm creepage between associated copper areas.

How does the iLOCK pin affect interlocking behavior when tied to GND versus VDD?

When iLOCK is tied to VDD, interlocking is enabled: if INA and INB are both high, both GOUT_A and GOUT_B are forced low to prevent shoot-through. When iLOCK is tied to GND, interlocking is disabled, allowing simultaneous high outputs - required for synchronous rectification or paralleled switch configurations. No external pull-up/down resistors are needed; internal biasing ensures clean logic levels.

Can STGAP2DM drive SiC MOSFETs with negative gate turn-off voltage?

Yes - STGAP2DM supports bipolar gate driving: connect VH_A to +20 V and GNDISO_A to –5 V to achieve –5 V turn-off bias. The device's rail-to-rail output stage and 26 V absolute max VH rating accommodate this configuration. Ensure external gate resistors and local filtering capacitors are sized for SiC's higher dI/dt, and verify that the chosen negative rail remains within the ±1500 V differential limit relative to other isolated grounds.

What happens to GOUT outputs during VDD undervoltage or loss?

When VDD falls below operational range (≤3.1 V), the control logic enters safe state: both GOUT_A and GOUT_B are actively driven low, regardless of input pin states. This behavior is enforced by an internal watchdog that detects LV-side communication loss and overrides output logic - ensuring fail-safe shutdown even if the MCU freezes or loses power before issuing a shutdown command.