My Inquiry
My Account
STMicroelectronics STGAP2DMTR
- Part No.:
- STGAP2DMTR
- Manufacturer:
- STMicroelectronics
- Category:
- Isolators - Gate Drivers
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
STGAP2DMTR.pdf
- Description:
- DGTL ISO 1.7KV 2CH GATE DVR 16SO
- Quantity:
- Payment:
- Shipping:
Inventory:2,935
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STGAP2DMTR from STMicroelectronics is a galvanically isolated dual-channel 4 A half-bridge gate driver IC for high-voltage power stages, featuring 1700 V isolation, ±100 V/ns CMTI, 75 ns max propagation delay, and integrated UVLO, thermal shutdown, interlocking, and standby functions - deployed in industrial motor drives, UPS inverters, and PFC circuits.
For engineers reviewing the STGAP2DMTR datasheet, STGAP2DMTR pinout, STGAP2DMTR application, or STGAP2DMTR equivalent, key selection criteria include channel isolation integrity, rail-to-rail 4 A sink/source capability, configurable interlock logic, dedicated SD/BRAKE control, and SO-16 package compatibility with high-voltage PCB layout constraints.
Technical Context
The STGAP2DMTR implements two independent isolated gate driving channels (A and B) with separate VH_A/VH_B supplies and GNDISO_A/GNDISO_B references, enabling unipolar or bipolar gate drive configurations. Its input-to-output isolation meets UL 1577 (4000 VPEAK) and VDE 0884-11 (1750 VPEAK) standards, with 4 mm creepage/clearance and CTI ≥ 400 V.
Control logic uses 3.3 V/5 V TTL/CMOS-compatible inputs with hysteresis and deglitch filtering (20–40 ns), while output stage delivers rail-to-rail switching with <1.5 Ω RDS(on) (source/sink), 110–120 mV low-level voltage, and active clamp limiting (SafeClp = 2.0–2.3 V) during UVLO conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Voltage | 1700 V DC or peak; enables safe operation between 600/1200 V IGBTs/MOSFETs and low-voltage MCU control domains. |
| Output Drive Current | 4 A sink/source at 25 °C; supports fast switching of high-Qg power devices up to 1 MHz in hard-switched topologies. |
| Propagation Delay | 75 ns typ. (max 90 ns); ensures precise PWM timing alignment between channels for reduced shoot-through risk. |
| CMTI | ±100 V/ns; maintains signal integrity in noisy high-dV/dt environments like motor phase-leg commutation. |
| UVLO Threshold | VH turn-on: 9.1 V typ., hysteresis 0.75 V; prevents erratic gate behavior during supply ramp-up/down. |
| Thermal Shutdown | Triggers at 170 °C junction temp with 20 °C hysteresis; protects against sustained overload or poor heatsinking. |
| Standby Quiescent Current | 40–80 µA on VDD, 400–550 µA per VH rail; reduces idle power in battery-backed or energy-sensitive systems. |
Pinout & Package
STGAP2DMTR is housed in a SO-16 narrow-body surface-mount package (9.8 × 6.0 mm, 1.27 mm pitch) with reinforced creepage/clearance (4 mm) and ECOPACK® environmental compliance.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 VDD | Logic supply input | Powers 3.3/5 V control logic; requires local 100 nF + 1–10 µF bypassing to suppress digital noise coupling. |
| 2 INA / 3 INB | Channel A/B logic inputs | Active-high TTL/CMOS signals controlling respective GOUT outputs; deglitched (20–40 ns) to reject EMI. |
| 4 SD | Shutdown input | Active-low global disable; forces both outputs to safe state (low) independent of other inputs. |
| 5 BRAKE | Brake input | Active-low signal forcing both GOUTs low - used for emergency motor stop or short-circuit protection. |
| 6 iLOCK | Interlock enable/disable | Connect to VDD to enforce mutual exclusion (A/B never high simultaneously); connect to GND to disable. |
| 7 GND | Logic ground reference | Common return for VDD and all logic inputs; must be separated from isolated grounds to preserve isolation barrier. |
| 9 VH_B / 14 VH_A | High-side gate supply rails | Provide up to 26 V to floating output stages; each requires dedicated 100 nF + 1–10 µF local decoupling. |
| 10 GOUT_B / 15 GOUT_A | Gate drive outputs | Rail-to-rail 4 A sink/source outputs; actively clamped to ≤2.3 V during UVLO to prevent partial turn-on. |
| 11 GNDISO_B / 16 GNDISO_A | Floating output grounds | Isolated return paths for VH_B/VH_A; differential voltage limit ±1500 V ensures robustness in split-rail topologies. |
Key Features
| Feature | Design Value |
|---|---|
| Dual isolated gate drivers | Independent VH_A/GNDISO_A and VH_B/GNDISO_B supplies support asymmetric or negative gate biasing in half-bridge designs. |
| Configurable interlocking | iLOCK pin allows hardware-selectable shoot-through prevention - critical for reliability in IGBT-based motor drives. |
| Dedicated safety pins | SD (global shutdown) and BRAKE (forced low) provide redundant, deterministic fault response without software intervention. |
| Integrated UVLO + thermal shutdown | Prevents device damage under brownout or overload; automatic recovery after temperature or supply stabilization. |
| Low-power standby mode | Reduces total quiescent current to <1 mA; entered via timed SD/INA/INB/BRAKE sequence, exited with wake-up delay <200 µs. |
Applications
| Industrial Motor Drives | Uninterruptible Power Supplies |
|---|---|
|
Use Scenario: Driving 1200 V IGBTs in three-phase VFDs for pumps, compressors, and conveyors. IC Role / Device Role / Timing Role: Isolated half-bridge gate driver providing synchronized, shoot-through-protected switching with <75 ns delay matching. Use Value: Enables >98% efficiency at 10–20 kHz switching while maintaining >1700 V isolation across motor phase-to-ground barriers. |
Use Scenario: Controlling bidirectional DC-AC and AC-DC stages in online double-conversion UPS systems. IC Role / Device Role / Timing Role: Dual-channel gate driver managing inverter and rectifier legs with independent UVLO and thermal monitoring per channel. Use Value: Supports seamless transfer between utility and battery modes with <200 µs wake-up from standby and ±100 V/ns noise immunity. |
| Power Factor Correction | Induction Heating |
|
Use Scenario: Driving interleaved boost MOSFETs in active PFC front-ends for server PSUs and EV chargers. IC Role / Device Role / Timing Role: High-CMTI gate driver ensuring clean turn-on/turn-off despite high di/dt in boost inductors and EMI filters. Use Value: Maintains stable regulation at >100 kHz with <20 ns pulse width distortion and rail-to-rail 4 A drive into high-Ciss devices. |
Use Scenario: Switching resonant LLC or Class-D inverter bridges in domestic and industrial induction cooktops. IC Role / Device Role / Timing Role: Isolated gate driver delivering precise dead-time control and fast 30 ns rise/fall times into high-frequency GaN/IGBT loads. Use Value: Enables >90% thermal efficiency at 20–100 kHz with active clamp limiting preventing gate oxide overstress during ZVS transitions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8239AD-IS | 2.5 A drive strength, 1500 V isolation, no interlock pin, 100 ns max delay | Lacks hardware interlock and dedicated BRAKE pin; suited for lower-power, non-safety-critical inverters | Select when system-level shoot-through protection is handled by MCU firmware and peak current <3 A suffices. |
| UCC5390SCD | 4 A drive, 5000 VPK isolation, integrated Miller clamp, no standby mode | Higher isolation rating but no low-power standby; optimized for high-reliability automotive traction inverters | Choose for ASIL-B systems requiring enhanced isolation margin and Miller clamping, where continuous operation is mandatory. |
Compared with Si8239AD-IS and UCC5390SCD, STGAP2DMTR uniquely balances 4 A drive, 1700 V isolation, hardware interlock, and sub-1 mA standby - making it optimal for cost-sensitive industrial drives needing both safety and energy efficiency.
Availability
STGAP2DMTR is available at Aetrix Electronics and suitable for industrial motor drives, uninterruptible power supplies, and power factor correction systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for STGAP2DMTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog components for industrial, automotive, and consumer markets.
STGAP2DMTR belongs to ST's STGAP family of isolated gate drivers - engineered specifically for robust, high-efficiency switching in industrial motor control, UPS, and renewable energy inverters where safety, reliability, and thermal resilience are critical.
FAQ
What is the maximum recommended switching frequency for STGAP2DMTR?
The datasheet specifies a maximum switching frequency of 1 MHz under recommended operating conditions. However, practical limits depend on power dissipation and junction temperature: at 25 °C ambient with adequate heatsinking, reliable operation is achieved up to 500 kHz in 1200 V IGBT half-bridges. Above this, thermal derating becomes necessary due to 1.16 W output-stage power dissipation.
How does the interlocking function behave when iLOCK is left floating?
The iLOCK pin has an internal pull-up resistor (66–142 kΩ), so if left unconnected, it defaults to VDD logic level - enabling interlocking. This ensures that GOUT_A and GOUT_B cannot be high simultaneously unless iLOCK is explicitly tied to GND. No external pull-up is required for default-safe operation.
Can STGAP2DMTR drive both N-channel and P-channel high-side switches?
Yes - its rail-to-rail outputs and flexible VH_x supply allow unipolar (e.g., N-channel with bootstrap or isolated supply) or bipolar (e.g., P-channel with negative gate bias) configurations. The datasheet Figure 3 confirms compatibility with both, provided VH_x is set to appropriate voltage (e.g., −5 V to +15 V relative to GNDISO_x) and local decoupling is applied.
What happens to GOUT outputs during VDD power loss while VH_A/VH_B remain powered?
The watchdog function detects loss of VDD and forces both GOUT outputs into safe state (low) within microseconds. This prevents unintended turn-on of power devices due to floating logic inputs, ensuring fail-safe behavior even when only the isolated side remains energized - a critical feature for industrial safety compliance.
STGAP2DMTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Magnetic Coupling
- Number of Channels:
- 2
- Voltage - Isolation:
- 1700VDC
- Common Mode Transient Immunity (Min):
- 100V/ns
- Propagation Delay tpLH / tpHL (Max):
- 100ns, 100ns
- Pulse Width Distortion (Max):
- 20ns
- Rise / Fall Time (Typ):
- 30ns, 30ns
- Current - Output High, Low:
- 4A, 4A
- Current - Peak Output:
- -
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 3V ~ 5.5V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
- Approval Agency:
- -
STGAP2DMTR FAQ
1.How can I place an order for STGAP2DMTR through Aetrix?
Please submit a Request for Quotation (RFQ) for STGAP2DMTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STGAP2DMTR reliable?
The price and inventory of STGAP2DMTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STGAP2DMTR is usually 5 days.
3.What payment methods are accepted for STGAP2DMTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STGAP2DMTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STGAP2DMTR?
STGAP2DMTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STGAP2DMTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STGAP2DMTR?
For technical support, including STGAP2DMTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STGAP2DMTR requirements.
6.How does Aetrix verify that STGAP2DMTR is sourced from the original manufacturer or authorized distributors?
All STGAP2DMTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STGAP2DMTR meets industry standards.
7.What is the process for return or replacement of STGAP2DMTR?
All STGAP2DMTR units undergo pre-shipment inspection (PSI). If there is an issue with STGAP2DMTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STGAP2DMTR part is unused and in its original packaging.
Return procedure for STGAP2DMTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STGAP2DMTR Tags
.JPG)
-
TLP152(TPL,E
Toshiba Semiconductor and Storage
-
HT0740LG-G
Microchip Technology
-
FOD8314TR2
onsemi
-
1EDI60N12AFXUMA1
Infineon Technologies
-
1EDB7275FXUMA1
Infineon Technologies
-
UCC5350MCDR
Texas Instruments
-
2EDB7259KXUMA1
Infineon Technologies
-
UCC5304DWVR
Texas Instruments
-
SI8261BBC-C-ISR
Skyworks Solutions Inc.
-
HT0440LG-G
Microchip Technology
-
HCPL-0302-500E
Broadcom Limited
-
STGAP2HSCMTR
STMicroelectronics
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
