STMicroelectronics STGAP2GSCTR

Overview

STGAP2GSCTR from STMicroelectronics is a galvanically isolated single-channel gate driver IC optimized for enhancement-mode GaN FETs, featuring 2 A source / 3 A sink peak output current, 100 V/ns CMTI, 45 ns max input-output propagation delay, and rail-to-rail outputs in a wide-body SO-8W package. It enables high-efficiency, high-frequency motor inverters and DC-DC converters by supporting independent turn-on/turn-off control via dedicated GON/GOFF pins and GaN-optimized UVLO (4.2–4.8 V turn-on).

For engineers reviewing the STGAP2GSCTR datasheet, STGAP2GSCTR pinout, STGAP2GSCTR application, or STGAP2GSCTR equivalent, key selection criteria include isolation rating (3.5 kVRMS), bipolar/unipolar gate drive flexibility, thermal shutdown (170 °C), standby mode (550 µA VH quiescent current), and compatibility with 3.3 V/5 V TTL/CMOS logic inputs with hysteresis.

Technical Context

The STGAP2GSCTR integrates dual-input logic control (IN+, IN−) with hardware interlocking to prevent cross-conduction, and implements a watchdog function that forces outputs into safe state (GOFF active, GON high-Z) during LV-side power loss or communication failure. Its isolated floating section supports up to 15 V gate drive voltage (VH) with 1.2 kVPEAK repetitive isolation voltage and IEC 60747-17 certification.

Propagation delay is tightly controlled at 35–50 ns (typ.) across temperature and supply conditions, with pulse width distortion ≤8 ns-critical for precise PWM timing in >1 MHz switching applications like wireless chargers and PFC stages. The device uses separate source (GON) and sink (GOFF) terminals to allow asymmetric gate resistor tuning for optimal GaN switching behavior.

Key Specifications

Pinout & Package

STGAP2GSCTR is housed in a wide-body SO-8W package (7.5 mm × 10.3 mm, 2.5 mm height) with creepage/clearance ≥8 mm and CTI ≥400 V, certified per IEC 60747-17 and UL 1577 for reinforced insulation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar isolated GaN gate driver applications.

Compared with UCC5870QDWJR and ADUM4135BRNZ, STGAP2GSCTR uniquely combines GaN-tuned UVLO, hardware interlock, and true dual-output architecture-enabling simpler, more robust designs for high-frequency, high-reliability GaN systems without external components.

Availability

STGAP2GSCTR is available at Aetrix Electronics and suitable for industrial motor inverters, wireless charging transmitters, server PSU PFC stages, and UPS half-bridge converters requiring stable component supply, full traceability, and long-term lifecycle support.

Supply support for STGAP2GSCTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog devices for industrial, automotive, and consumer markets.

STGAP2GSCTR belongs to ST's STGAP family of isolated gate drivers-engineered specifically for wide-bandgap power devices, with emphasis on GaN compatibility, high-speed timing accuracy, and reinforced safety certification.

FAQ

What is the maximum recommended switching frequency for STGAP2GSCTR?

The datasheet specifies a maximum switching frequency of 2 MHz under typical thermal conditions. This limit assumes adequate PCB layout (low-inductance gate loops), proper bypassing (100 nF + 1–10 µF per supply), and junction temperature maintained below 125 °C. At elevated temperatures or with insufficient heatsinking, derating is required per the thermal derating curves in DS14152 Rev 2 page 8.

How does the standby mode activate and recover?

Standby activates when both IN+ and IN− are held high for ≥280 µs (tSTBY max). Outputs enter safe state (GOFF active, GON high-Z) and quiescent currents drop to 65 µA (VDD) and 550 µA (VH). Recovery requires first applying any non-standby input combination for >280 ns (tstbyfilt), then returning to standby state for 10–35 µs (tWUP range) before normal operation resumes with <3 µs wake-up delay (tawake).

Can STGAP2GSCTR drive SiC MOSFETs as well as GaN FETs?

Yes-it supports SiC MOSFETs with gate thresholds up to ~4 V, though its UVLO turn-on threshold (4.5 V) is optimized for GaN's lower VGS(th) (~1.5–2.0 V). For SiC, verify that the gate drive voltage (up to 15 V) and sink current (3 A) meet the target device's Qg and Miller plateau requirements; the dual-output architecture remains beneficial for asymmetric switching control.

What layout practices are mandatory to achieve rated CMTI performance?

To sustain 100 V/ns CMTI, the PCB must isolate the primary (IN+/IN−/VDD/GND) and secondary (VH/GON/GOFF/GNDISO) sides with ≥8 mm creepage/clearance, avoid copper under the IC body, use dedicated inner-plane return paths for gate current (Kelvin-source routing), and place 100 nF ceramic capacitors within 2 mm of VDD-GND and VH-GNDISO pins. Splitting ground planes between logic and isolated sections is essential.