STMicroelectronics STGAP2GSNC

Overview

STGAP2GSNC from STMicroelectronics is a high-voltage isolated single-channel gate driver optimized for enhancement-mode GaN FETs, featuring 2 A source / 3 A sink peak output current, ±100 V/ns common-mode transient immunity (CMTI), 45 ns input-output propagation delay, and rail-to-rail outputs. It integrates UVLO with GaN-optimized thresholds (VHon = 4.5 V, VHoff = 4.4 V), thermal shutdown (TSD = 170 °C), and standby mode for low idle power - deployed in industrial motor inverters and high-frequency DC-DC converters.

For engineers reviewing the STGAP2GSNC datasheet, STGAP2GSNC pinout, STGAP2GSNC application, or STGAP2GSNC equivalent, key selection criteria include its dedicated GON/GOFF outputs enabling independent turn-on/turn-off control, SO-8 narrow-body isolation package with 4 mm creepage/clearance, and compatibility with 3.3 V/5 V TTL/CMOS logic inputs with hysteresis - critical for noise-immune GaN gate driving in >1 MHz switching topologies.

Technical Context

The STGAP2GSNC implements galvanic isolation between low-voltage control logic (VDD/GND) and high-voltage gate-driving side (VH/GNDISO), supporting up to 1700 V working voltage (VISO-OP) and 2828 VRMS isolation withstand. Its dual-input architecture (IN+, IN−) enables hardware interlocking and polarity selection, while the separate GON (source) and GOFF (sink) outputs allow asymmetric gate resistor tuning to suppress GaN-induced spurious turn-on during high dV/dt transients.

Functional safety features include a watchdog that forces safe state (GOFF active, GON high-Z) when VDD is unpowered or communication fails, plus UVLO with 100 mV hysteresis and thermal shutdown with 20 °C hysteresis. The device supports both unipolar and bipolar gate drive configurations via external VH/VL supply routing, and enters standby mode when both inputs are held high for >280 µs - reducing VDD and VH quiescent current to 65 µA and 550 µA respectively.

Key Specifications

Pinout & Package

Narrow-body SO-8 package (ECOPACK®, 4 mm creepage/clearance) with reinforced galvanic isolation between primary (control) and secondary (power) sides.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar isolated GaN gate driver applications.

Compared with UCC5870-Q1 and ADUM4135, STGAP2GSNC uniquely combines GaN-optimized UVLO, true independent GON/GOFF outputs, and ultra-low standby current - making it the only choice for cost-sensitive, high-efficiency industrial GaN inverters requiring <100 µA idle draw and hardware interlock.

Availability

STGAP2GSNC is available at Aetrix Electronics and suitable for industrial motor drives, high-frequency DC-DC converters, and wireless power transmitters requiring stable component supply, long-term lifecycle support, and traceable sourcing for production ramp.

Supply support for STGAP2GSNC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog/mixed-signal devices for industrial, automotive, and consumer markets.

STGAP2GSNC belongs to ST's STGAP family of isolated gate drivers - engineered specifically for wide-bandgap power devices, with emphasis on GaN compatibility, high-speed timing fidelity, and robust fault handling in high-reliability industrial power conversion.

FAQ

What is the maximum recommended switching frequency for STGAP2GSNC?

The datasheet specifies a maximum switching frequency of 2 MHz under thermal limits, but practical use is constrained by power dissipation and PCB layout. At 1 MHz with 3 A sink current and 100 ns total propagation uncertainty, junction temperature remains below 125 °C with standard JEDEC 2s2p board cooling - verified in ST's reference design AN5752.

Can STGAP2GSNC drive SiC MOSFETs?

Yes, STGAP2GSNC can drive SiC MOSFETs, but its UVLO thresholds (4.5 V turn-on) are higher than typical SiC VGS(th) (2.5–4.0 V), risking incomplete turn-off if gate voltage droops near threshold. For SiC, ST recommends STGAP2SIC instead - which features 2.8 V UVLO and enhanced Miller clamping.

How does the standby mode activate and deactivate?

Standby activates when both IN+ and IN− are held high for ≥280 µs; outputs enter safe state (GOFF active, GON high-Z) and quiescent currents drop to 65 µA (VDD) and 550 µA (VH). To exit, inputs must transition to any non-high combination for >280 ns, then return to high for 10–35 µs - after which GON/GOFF respond to input state with 1–3 µs wake-up delay.

What layout practices prevent gate ringing with STGAP2GSNC?

Minimize gate loop inductance by placing 10 kΩ pull-down resistor directly at GaN Kelvin-source pin, routing GON/GOFF traces over dedicated inner-plane return paths, using multiple vias for VH/GNDISO connections, and mounting 100 nF ceramic capacitors ≤2 mm from each supply pin. ST's layout guide AN5752 shows measured ringing reduction from 8.2 V to <0.5 V using these techniques.