STMicroelectronics STGAP2GSNCTR

Overview

STGAP2GSNCTR from STMicroelectronics is a reinforced-isolated single-channel gate driver IC optimized for enhancement-mode GaN FETs, featuring 2 A source / 3 A sink peak output current, ±100 V/ns common-mode transient immunity (CMTI), 45 ns input-output propagation delay, and rail-to-rail outputs in a narrow-body SO-8 package. It enables high-efficiency motor inverters and DC-DC converters by supporting independent turn-on/turn-off control via dedicated GON/GOFF pins and UVLO thresholds tuned for GaN threshold voltages.

For engineers reviewing the STGAP2GSNCTR datasheet, STGAP2GSNCTR pinout, STGAP2GSNCTR application, or STGAP2GSNCTR equivalent, key selection criteria include GaN-specific UVLO hysteresis (100 mV), dual-input hardware interlock capability, thermal shutdown at 170 °C, standby quiescent current as low as 40 µA on VDD, and isolation rating up to 4800 V_PEAK surge voltage.

Technical Context

This driver implements galvanic isolation between logic-side (VDD/GND/IN+/IN−) and power-side (VH/GNDISO/GON/GOFF) domains using ST's proprietary reinforced insulation technology. Its dual-input architecture supports active-high (IN+) and active-low (IN−) control with built-in hardware interlocking to prevent cross-conduction during controller faults.

The device integrates independent source (GON) and sink (GOFF) outputs with R_DS(on) of 1.5 Ω (source) and 0.8 Ω (sink) at 100 mA, enabling precise gate loop tuning for GaN HEMTs. UVLO thresholds (VHon = 4.5 V, VHoff = 4.4 V) and thermal shutdown (TSD = 170 °C, hysteresis = 20 °C) are calibrated specifically for GaN reliability under fast dV/dt transients.

Key Specifications

Pinout & Package

Narrow-body SO-8 package (ECOPACK® compliant, 4 mm creepage/clearance, reinforced isolation).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar isolated GaN gate driver applications.

Compared with UCC5870-Q1 and ADUM4135, STGAP2GSNCTR delivers GaN-optimized UVLO, true dual-output flexibility for asymmetric gate driving, and lower propagation delay-making it uniquely suited for high-frequency, high-reliability GaN power stages where timing precision and intrinsic fault protection are design-critical.

Availability

STGAP2GSNCTR is available at Aetrix Electronics and suitable for industrial motor inverters, high-frequency DC-DC converters, wireless power transmitters, and uninterruptible power supplies requiring stable component supply across long-lifecycle production programs.

Supply support for STGAP2GSNCTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog components for industrial, automotive, and consumer markets.

STGAP2GSNCTR belongs to ST's STGAP family of isolated gate drivers, engineered specifically to address the timing, isolation, and protection challenges of enhancement-mode GaN FETs in high-efficiency power conversion systems.

FAQ

What is the purpose of the dual IN+ and IN− inputs?

The dual inputs implement hardware-level interlocking: only the "IN+ high / IN− low" state activates GON, while "IN+ low / IN− high" activates GOFF. All other combinations force GOFF ON and GON high-impedance-preventing shoot-through during controller failure or signal corruption. This eliminates reliance on software-based dead-time generation.

Can STGAP2GSNCTR drive SiC MOSFETs?

Yes, but with design caveats: its 15 V max VH and GaN-tuned UVLO (4.4–4.5 V) are compatible with most SiC devices, though SiC typically benefits from higher gate drive voltage (18–20 V) and wider UVLO hysteresis. The 2 A/3 A drive strength suffices for ≤60 mΩ SiC FETs; for higher capacitance devices, external buffer stages may be needed.

How does the standby function affect output behavior?

In standby mode-activated by holding both IN+ and IN− high for >200 µs-the driver forces GOFF into active-sink (low) state and places GON in high-impedance. This actively pulls the GaN gate to GNDISO, ensuring safe turn-off while reducing VDD current to 40–65 µA and VH current to 400–550 µA.

What layout practices are essential for reliable GaN operation?

Minimize gate loop inductance by placing 10 kΩ pull-down resistors directly at the GaN Kelvin-source pin, routing GNDISO return paths on inner planes beneath gate resistors, and using separate vias for VH/GNDISO near the IC. Place 100 nF ceramic capacitors <2 mm from VDD-GND and VH-GNDISO pins, plus 1–10 µF bulk caps nearby-no traces under the SO-8 body.