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STMicroelectronics STGAP2HDMTR
- Part No.:
- STGAP2HDMTR
- Manufacturer:
- STMicroelectronics
- Category:
- Isolators - Gate Drivers
- Package:
- 36-BSOP (0.295", 7.50mm Width), 32 Leads
- Datasheet:
-
STGAP2HDMTR.pdf
- Description:
- DIGITAL ISO 6KV 2CH GT DVR 36SO
- Quantity:
- Payment:
- Shipping:
Inventory:1,375
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Product details
Overview
STGAP2HDMTR from STMicroelectronics is a galvanically isolated dual-channel gate driver IC for high-reliability half-bridge power stages, featuring 4 A sink/source drive strength per channel, 100 V/ns CMTI, 75 ns max propagation delay, and integrated Miller clamp, UVLO, thermal shutdown, and configurable interlocking - deployed in industrial motor drives, UPS inverters, and PFC modules.
For engineers reviewing the STGAP2HDMTR datasheet, STGAP2HDMTR pinout, STGAP2HDMTR application, or STGAP2HDMTR equivalent, key selection criteria include isolation voltage (3.5 kVRMS), dual-channel independent turn-on/turn-off control via separate GOFF/GON pins, 26 V gate drive capability, TTL/CMOS-compatible 3.3 V/5 V inputs with hysteresis, and standby mode for idle power reduction.
Technical Context
The STGAP2HDMTR implements two fully isolated gate driving channels with independent floating supplies (VH_A/VH_B) and dedicated isolated grounds (GNDISO_A/GNDISO_B), enabling operation across ±1700 V differential potential between channels. Each channel integrates rail-to-rail output buffers with 4 A peak current, Miller clamp circuitry (VCLAMPth = 1.3–2.6 V), and active low-side clamping to suppress gate spikes during fast commutation.
Its interlocking function-enabled by iLOCK pin logic level-prevents simultaneous high-state outputs to avoid shoot-through in half-bridge topologies; this protection can be disabled for parallel channel operation. Propagation delay matching (MT ≤ 20 ns) and deglitch filtering (20–40 ns) ensure robust PWM timing integrity in noisy industrial environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CMTI | 100 V/ns - immune to fast common-mode transients in high-dV/dt inverter legs |
| Propagation Delay | 75 ns max - enables precise <1 MHz PWM control with tight timing margins |
| Output Current | 4 A sink/source - drives large GaN/SiC MOSFETs and IGBTs without external boost |
| Isolation Voltage | 3.5 kVRMS (IEC 60747-17, UL 1577) - certified basic insulation for industrial safety compliance |
| UVLO Threshold | VHon = 9.1 V typ, VHoff = 8.4 V typ - 750 mV hysteresis prevents oscillation near supply brownout |
| Miller Clamp | VCLAMPth = 2.0 V typ - actively clamps gate voltage below threshold during dV/dt-induced coupling |
| Standby Current | 40–80 µA on VDD, 400–550 µA on VH - reduces idle power in energy-sensitive systems |
Pinout & Package
STGAP2HDMTR uses a wide-body SO-36W package with reinforced galvanic isolation barrier separating control-side (GND/VDD/INA/INB/SD/BRAKE/iLOCK) and two independent isolated power domains (Channel A: VH_A/GNDISO_A/GON_A/GOFF_A/CLAMP_A; Channel B: VH_B/GNDISO_B/GON_B/GOFF_B/CLAMP_B). All N.C. pins must remain unconnected; both GNDISO_A pins require shorting and low-inductance PCB routing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, GND | Control logic supply | 5.5 V max logic rail; powers input buffers, interlock logic, and digital state machine |
| INA, INB | Channel A/B input | Active-high TTL/CMOS inputs with 0.33·VDD low threshold and 0.66·VDD high threshold |
| SD, BRAKE | Global control | Active-low shutdown and brake override - forces safe state (GOFF ON, GON Hi-Z) immediately |
| iLOCK | Interlock config | Connect to VDD to enable shoot-through prevention; connect to GND to disable for parallel operation |
| VH_A, GNDISO_A | Channel A gate supply | 26 V max floating supply; powers GON_A/GOFF_A/CLAMP_A - requires local 100 nF + 1–10 µF decoupling |
| GON_A, GOFF_A | Channel A outputs | Separate source/sink terminals - allow independent gate resistor tuning for optimized switching dv/dt |
| CLAMP_A | Channel A Miller clamp | Clamps gate node to ≤2.6 V when VGS exceeds threshold - suppresses false turn-on in high-side switches |
| VH_B, GNDISO_B | Channel B gate supply | Independent floating rail identical to Channel A - supports asymmetric or bipolar gate drive configurations |
Key Features
| Feature | Design Value |
|---|---|
| Dual isolated gate drivers | Two independent 4 A channels with separate VH/GNDISO supplies - enables true half-bridge or dual-leg control |
| Configurable interlocking | Hardware-enforced shoot-through prevention via iLOCK pin - disableable for synchronous rectification or paralleled FETs |
| Integrated Miller clamp | Active clamp at 2.0 V typ - eliminates need for external diode/resistor networks in high-speed SiC/GaN designs |
| Thermal shutdown & UVLO | 170 °C junction shutdown with 20 °C hysteresis; 9.1 V/8.4 V UVLO thresholds - ensures fail-safe gate behavior under fault conditions |
| Low-power standby mode | Enters safe state (GOFF active, GON Hi-Z) with sub-100 µA total quiescent draw - ideal for intermittent-operation systems |
Applications
| Industrial Motor Drives | Uninterruptible Power Supplies |
|---|---|
|
Use Scenario: Driving 600–1200 V IGBTs in three-phase VFDs for pumps, compressors, and conveyors. IC Role / Device Role / Timing Role: Dual-channel isolated gate driver providing independent turn-on/turn-off control and shoot-through protection in half-bridge legs. Use Value: 100 V/ns CMTI ensures reliable operation in high-noise factory environments; 75 ns propagation delay supports >500 kHz PWM for torque ripple reduction. |
Use Scenario: Controlling bidirectional DC-AC and AC-DC conversion stages in online double-conversion UPS systems. IC Role / Device Role / Timing Role: Galvanically isolated gate driver managing high-side and low-side switches in inverter and rectifier bridges. Use Value: 3.5 kVRMS isolation meets IEC 62040-1 safety requirements; standby mode cuts idle losses during battery-backup operation. |
| Power Factor Correction | Induction Heating |
|
Use Scenario: Driving totem-pole or interleaved boost MOSFETs in high-efficiency server PSU PFC stages. IC Role / Device Role / Timing Role: High-current dual gate driver enabling zero-voltage switching (ZVS) control with precise dead-time management. Use Value: Separate GOFF/GON pins allow asymmetric gate resistors for optimized ZVS turn-on and hard-switched turn-off; 4 A drive sustains fast dV/dt in GaN-based designs. |
Use Scenario: Switching resonant half-bridge inverters in domestic and industrial induction cooktops and heating systems. IC Role / Device Role / Timing Role: Isolated driver delivering synchronized, high-current gate pulses to SiC MOSFETs operating at 20–100 kHz. Use Value: Miller clamp prevents spurious turn-on from transformer leakage coupling; thermal shutdown protects against coil overtemperature faults. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8239x-B-IS | 3.75 kVRMS isolation, 4 A drive, but no Miller clamp or interlocking; 120 ns max propagation delay | Lacks hardware shoot-through prevention and active Miller clamping - requires external circuitry for SiC/GaN reliability | Preferred where cost sensitivity outweighs need for integrated protection; suitable for legacy Si MOSFET designs |
| UCC5390SCD | 5 kVRMS isolation, 4 A drive, integrated Miller clamp, but single-channel output with dual-input logic | Requires two devices for half-bridge; lacks independent channel interlocking - relies on controller-level coordination | Better for space-constrained layouts needing highest isolation rating; adds system-level complexity for shoot-through avoidance |
Compared with Si8239x-B-IS and UCC5390SCD, STGAP2HDMTR uniquely combines dual-channel integration, hardware interlocking, and per-channel Miller clamping in a single SO-36W package - reducing BOM count, PCB area, and design risk in high-reliability industrial inverters.
Availability
STGAP2HDMTR is available at Aetrix Electronics and suitable for industrial motor drives, uninterruptible power supplies, and power factor correction systems requiring stable component supply, long-term lifecycle support, and certified galvanic isolation.
Supply support for STGAP2HDMTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, analog, MEMS, and microcontroller technologies for industrial, automotive, and consumer markets.
STGAP2HDMTR belongs to ST's STGAP family of reinforced-isolation gate drivers, engineered specifically for high-efficiency, high-reliability power conversion in industrial motor control and energy infrastructure applications.
FAQ
What is the maximum gate drive voltage supported by STGAP2HDMTR?
The STGAP2HDMTR supports up to 26 V on its VH_A and VH_B pins relative to their respective isolated grounds (GNDISO_A/GNDISO_B). This allows direct driving of SiC MOSFETs requiring higher gate voltages and accommodates bipolar gate drive configurations with negative turn-off bias. Absolute maximum rating is 28 V, but recommended operating condition is ≤26 V for reliability and thermal margin.
How does the interlocking function prevent shoot-through, and can it be disabled?
The interlocking function monitors INA and INB states and forces both GOUT_A and GOUT_B low if both inputs are high simultaneously - preventing concurrent conduction in half-bridge legs. It is enabled by pulling the iLOCK pin to VDD; connecting iLOCK to GND disables interlocking, allowing independent channel control for applications like synchronous rectification or paralleled FETs.
What is the purpose of the Miller clamp, and at what voltage does it activate?
The Miller clamp actively limits the gate-source voltage of the driven power device during high dV/dt transitions, preventing false turn-on caused by capacitive coupling. It activates when the CLAMP pin voltage exceeds VCLAMPth = 1.3–2.6 V (typical 2.0 V), clamping the gate node to a safe sub-threshold level. This eliminates need for external Miller clamp diodes in SiC/GaN designs.
Does STGAP2HDMTR support negative gate driving, and how is it implemented?
Yes - STGAP2HDMTR supports negative gate driving via separate VH and VL connections in bipolar configuration. By referencing GNDISO_A/B to a negative rail (e.g., –5 V), GOFF_A/B can pull the gate below source potential for enhanced noise immunity and faster turn-off. The datasheet Figure 5 explicitly shows unipolar and bipolar topologies, and CLAMP functionality remains active regardless of polarity.
STGAP2HDMTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 36-BSOP (0.295", 7.50mm Width), 32 Leads
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Number of Channels:
- 2
- Voltage - Isolation:
- 6000Vrms
- Common Mode Transient Immunity (Min):
- 100V/ns
- Propagation Delay tpLH / tpHL (Max):
- 90ns, 90ns
- Pulse Width Distortion (Max):
- -
- Rise / Fall Time (Typ):
- 30ns, 30ns
- Current - Output High, Low:
- 4A, 4A
- Current - Peak Output:
- 4A
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 3.1V ~ 5.5V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 36-SO
- Approval Agency:
- UL, VDE
STGAP2HDMTR FAQ
1.How can I place an order for STGAP2HDMTR through Aetrix?
Please submit a Request for Quotation (RFQ) for STGAP2HDMTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STGAP2HDMTR reliable?
The price and inventory of STGAP2HDMTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STGAP2HDMTR is usually 5 days.
3.What payment methods are accepted for STGAP2HDMTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STGAP2HDMTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STGAP2HDMTR?
STGAP2HDMTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STGAP2HDMTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STGAP2HDMTR?
For technical support, including STGAP2HDMTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STGAP2HDMTR requirements.
6.How does Aetrix verify that STGAP2HDMTR is sourced from the original manufacturer or authorized distributors?
All STGAP2HDMTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STGAP2HDMTR meets industry standards.
7.What is the process for return or replacement of STGAP2HDMTR?
All STGAP2HDMTR units undergo pre-shipment inspection (PSI). If there is an issue with STGAP2HDMTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STGAP2HDMTR part is unused and in its original packaging.
Return procedure for STGAP2HDMTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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