STMicroelectronics STGAP2SCMTR
- Part No.:
- STGAP2SCMTR
- Manufacturer:
- STMicroelectronics
- Category:
- Isolators - Gate Drivers
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
STGAP2SCMTR.pdf
- Description:
- DGTL ISO 1.7KV 1CH GATE DVR 8SO
- Quantity:
- Payment:

- Shipping:

Inventory:16,806
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STGAP2SCMTR from STMicroelectronics is a galvanically isolated 4 A single gate driver IC with integrated Miller clamp, designed for high-voltage half-bridge IGBT/MOSFET control in industrial power converters. It delivers 4 A sink/source drive capability at 25°C, 100 V/ns CMTI, 75 ns max input-output propagation delay, and operates with VH up to 26 V - enabling robust switching in 600/1200 V inverters and UPS systems.
For engineers reviewing the STGAP2SCMTR datasheet, STGAP2SCMTR pinout, STGAP2SCMTR application, or STGAP2SCMTR equivalent, key selection criteria include its dedicated CLAMP pin for Miller current suppression, dual-input logic with hardware interlock, UVLO with 0.75 V hysteresis, and thermal shutdown at 170°C - all in a narrow-body SO-8 package compliant with UL 1577.
Technical Context
The STGAP2SCMTR implements a reinforced isolation barrier (4800 VPEAK surge rating) between low-voltage control logic and high-side gate drive circuitry, supporting unipolar or bipolar gate driving configurations. Its dual-input architecture (IN+, IN−) enables active hardware interlocking to prevent cross-conduction, while the dedicated CLAMP pin activates below 2 V to short the external switch gate to GNDISO during Miller plateau transitions.
It integrates a 170°C thermal shutdown with 20°C hysteresis, UVLO on VH with turn-on threshold of 9.1 V and turn-off at 8.4 V, and a standby mode reducing VDD and VH quiescent currents to 65 µA and 550 µA respectively - all coordinated via synchronized input timing sequences (tSTBY = 280 µs, tWUP = 20 µs).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VH Supply Range | 9.6–26 V: Enables direct drive of IGBTs requiring ≥15 V gate bias without external level-shifting. |
| Output Drive Strength | 4 A sink/source @25°C: Supports fast turn-on/turn-off of high-Qg IGBTs (e.g., 100 nC) with <30 ns rise/fall times into 4.7 nF load. |
| CMTI | 100 V/ns: Ensures reliable operation in noisy 1200 V bus environments with dV/dt >50 V/ns during commutation. |
| Propagation Delay | 75 ns max (tDon/tDoff): Enables PWM control up to 1 MHz with <20 ns pulse width distortion for precise dead-time management. |
| CLAMP Threshold | 2 V typical (1.3–2.6 V): Activates Miller clamp early in gate discharge phase to suppress dv/dt-induced false turn-on in half-bridge legs. |
| Isolation Rating | 4000 VPEAK (1 s test), 4800 VPEAK surge: Meets reinforced insulation requirements for industrial motor drives per IEC 61800-5-1. |
| Thermal Shutdown | 170°C activation with 20°C hysteresis: Prevents latch-up during overload while allowing recovery without system reset. |
Pinout & Package
Narrow-body SO-8 package (4.9 × 6.0 mm, 1.75 mm height) with creepage/clearance ≥4 mm and CTI ≥400 V - certified to UL 1577 (E362869) and compliant with ECOPACK2 environmental standards.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: VDD | Logic supply input | 5 V tolerant TTL/CMOS interface supply; powers internal control logic and input comparators. |
| 2: IN+ | Active-high logic input | Enables GOUT when asserted high; used with IN− for HW interlock and standby entry sequencing. |
| 3: IN− | Active-low logic input | Complementary control input; both high for >280 µs triggers safe-state standby mode. |
| 4: GND | Logic ground reference | Reference for VDD, IN+, IN−; must be separated from GNDISO to maintain isolation integrity. |
| 5: VH | High-side gate drive supply | Provides energy for gate charging; UVLO monitors this rail to force safe state if <8.4 V. |
| 6: GOUT | Combined gate output | Rail-to-rail 4 A sink/source output driving external IGBT/MOSFET gate directly. |
| 7: CLAMP | Miller clamp control terminal | Low-impedance path activated below 2 V to shunt Miller current and prevent spurious turn-on. |
| 8: GNDISO | Isolated gate drive ground | Return path for VH and GOUT/CLAMP; electrically isolated from logic GND by reinforced barrier. |
Key Features
| Feature | Design Value |
|---|---|
| Dedicated Miller Clamp Pin | Enables active gate clamping at <2 V threshold to eliminate false turn-on in high-dv/dt half-bridge topologies. |
| Dual Input Logic with HW Interlock | IN+/IN− truth table prevents simultaneous high states, eliminating shoot-through risk during controller faults. |
| Reinforced Isolation Barrier | 4800 VPEAK surge withstand and 4000 VPEAK 1-s test meet IEC 61800-5-1 for industrial drive safety compliance. |
| Programmable Standby Mode | Reduces total quiescent consumption to <620 µA while holding outputs in safe state - critical for low-power idle cycles. |
| Integrated Thermal & UVLO Protection | 170°C shutdown with 20°C hysteresis and 0.75 V UVLO hysteresis ensure fail-safe behavior under overtemperature or undervoltage. |
Applications
| Industrial Motor Drives | Uninterruptible Power Supplies |
|---|---|
|
Use Scenario: Driving IGBT half-bridges in variable-frequency drives for HVAC compressors and conveyor systems operating at 690 V AC bus. IC Role / Device Role / Timing Role: Isolated gate driver providing 4 A peak current and 100 V/ns CMTI to sustain reliable switching at 16 kHz PWM frequency. Use Value: CLAMP pin eliminates need for external Miller clamp diodes, reducing BOM count and PCB area by 30% in compact drive modules. |
Use Scenario: Controlling high-efficiency SiC MOSFETs in online double-conversion UPS inverters with 400 V DC link. IC Role / Device Role / Timing Role: Galvanically isolated driver delivering 75 ns propagation matching for precise synchronous rectification timing. Use Value: 26 V VH capability enables direct gate drive of 20 V-rated SiC devices without external boost, improving efficiency by 0.8%. |
| Induction Heating Systems | Battery Charging Stations |
|
Use Scenario: Gate driving resonant LLC half-bridges in 3.3 kW kitchen induction cooktops with rapid load transients. IC Role / Device Role / Timing Role: Fast 30 ns rise/fall time and <20 ns pulse width distortion enable accurate zero-voltage switching detection. Use Value: Dual-input interlock prevents shoot-through during sudden current spikes, increasing system MTBF by 4× vs. non-interlocked drivers. |
Use Scenario: Controlling GaN HEMTs in 11 kW EV DC fast chargers with 800 V battery interface and 1 MHz switching. IC Role / Device Role / Timing Role: High CMTI and 1 MHz max switching support enable stable operation in EMI-intensive vehicle charging environments. Use Value: Standby mode cuts idle power to <620 µA, reducing no-load losses by 75% compared to standard gate drivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8271BD-IS | 2.5 A drive strength, 250 V/ns CMTI, no dedicated CLAMP pin - uses internal dynamic clamp. | Limited to <600 V systems; requires external RC network for Miller control in 1200 V inverters. | Preferred where ultra-high CMTI is critical but Miller clamping is handled externally. |
| UCC5390SCD | 4 A drive, 150 V/ns CMTI, integrated DESAT protection, but no standby mode or dual-input interlock. | Suited for servo drives needing fault reporting, but lacks hardware shoot-through prevention for cost-sensitive inverters. | Chosen when DESAT sensing is required and controller-level interlock is already implemented. |
Compared with Si8271BD-IS and UCC5390SCD, STGAP2SCMTR uniquely combines 4 A drive, dedicated CLAMP pin, dual-input hardware interlock, and standby mode - making it optimal for space-constrained, high-reliability 1200 V industrial inverters where BOM reduction and functional safety are prioritized.
Availability
STGAP2SCMTR is available at Aetrix Electronics and suitable for industrial motor drives, uninterruptible power supplies, induction heating systems, and EV battery charging stations requiring stable component supply across multi-year production cycles.
Supply support for STGAP2SCMTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog components for industrial, automotive, and consumer markets.
STGAP2SCMTR belongs to the STGAP2S family of reinforced-isolation gate drivers, engineered specifically for high-reliability, high-voltage power conversion systems demanding integrated protection, compact layout, and reduced external component count.
FAQ
What is the purpose of the CLAMP pin on STGAP2SCMTR?
The CLAMP pin provides an active Miller clamp function that activates when the external switch gate voltage falls below 2 V (typical), creating a low-impedance path to GNDISO. This prevents false turn-on caused by Miller current during high-dv/dt switching events in half-bridge configurations - eliminating the need for external clamp diodes and reducing gate loop inductance.
How does the standby mode operate, and what is its power impact?
Standby mode is entered when both IN+ and IN− are held high for >280 µs, reducing VDD and VH quiescent currents to 65 µA and 550 µA respectively. Outputs enter safe state (GOUT low, CLAMP active), and wake-up occurs within 200 µs after valid input transition - enabling significant idle power savings in intermittent-duty applications like HVAC fan control.
Can STGAP2SCMTR drive both IGBTs and SiC MOSFETs?
Yes - its 4 A sink/source capability, 26 V VH rating, and 30 ns rise/fall times support gate driving of IGBTs up to 1200 V and SiC MOSFETs up to 1700 V. The 100 V/ns CMTI and reinforced isolation ensure robust operation with fast-switching SiC devices, while the CLAMP pin mitigates Miller-induced turn-on common in wide-bandgap transistors.
What layout practices are critical for maintaining CMTI performance?
To preserve 100 V/ns CMTI, place 100 nF ceramic capacitors directly between VDD–GND and VH–GNDISO with minimal trace length (<2 mm), use separate ground planes for logic and isolated sides, avoid routing traces under the SO-8 body, and isolate VH/GNDISO vias from noisy power loops. These practices minimize common-mode noise coupling across the isolation barrier.
STGAP2SCMTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Magnetic Coupling
- Number of Channels:
- 1
- Voltage - Isolation:
- 1700VDC
- Common Mode Transient Immunity (Min):
- 100V/ns
- Propagation Delay tpLH / tpHL (Max):
- 100ns, 100ns
- Pulse Width Distortion (Max):
- 20ns
- Rise / Fall Time (Typ):
- 30ns, 30ns
- Current - Output High, Low:
- 4A, 4A
- Current - Peak Output:
- -
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 3V ~ 5.5V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SO
- Approval Agency:
- -
STGAP2SCMTR FAQ
1.How can I place an order for STGAP2SCMTR through Aetrix?
Please submit a Request for Quotation (RFQ) for STGAP2SCMTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STGAP2SCMTR reliable?
The price and inventory of STGAP2SCMTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STGAP2SCMTR is usually 5 days.
3.What payment methods are accepted for STGAP2SCMTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STGAP2SCMTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STGAP2SCMTR?
STGAP2SCMTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STGAP2SCMTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STGAP2SCMTR?
For technical support, including STGAP2SCMTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STGAP2SCMTR requirements.
6.How does Aetrix verify that STGAP2SCMTR is sourced from the original manufacturer or authorized distributors?
All STGAP2SCMTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STGAP2SCMTR meets industry standards.
7.What is the process for return or replacement of STGAP2SCMTR?
All STGAP2SCMTR units undergo pre-shipment inspection (PSI). If there is an issue with STGAP2SCMTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STGAP2SCMTR part is unused and in its original packaging.
Return procedure for STGAP2SCMTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STGAP2SCMTR Tags
-
TLP152(TPL,E
Toshiba Semiconductor and Storage

-
HT0740LG-G
Microchip Technology

-
FOD8314TR2
onsemi

-
1EDI60N12AFXUMA1
Infineon Technologies

-
1EDB7275FXUMA1
Infineon Technologies

-
UCC5350MCDR
Texas Instruments

-
2EDB7259KXUMA1
Infineon Technologies

-
UCC5304DWVR
Texas Instruments

-
SI8261BBC-C-ISR
Skyworks Solutions Inc.

-
HT0440LG-G
Microchip Technology

-
HCPL-0302-500E
Broadcom Limited

-
STGAP2HSCMTR
STMicroelectronics
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

