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STMicroelectronics STGAP2SICDTR
- Part No.:
- STGAP2SICDTR
- Manufacturer:
- STMicroelectronics
- Category:
- Isolators - Gate Drivers
- Package:
- 36-BSOP (0.295", 7.50mm Width), 32 Leads
- Datasheet:
-
STGAP2SICDTR.pdf
- Description:
- DIGITAL ISO 6KV 2CH GT DVR 36SO
- Quantity:
- Payment:
- Shipping:
Inventory:1,844
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Product details
Overview
STGAP2SICDTR from STMicroelectronics is a galvanically isolated dual gate driver IC for SiC MOSFETs, delivering 4 A sink/source drive capability per channel, 100 V/ns CMTI, and 75 ns max input-output propagation delay. It features separate source/sink outputs, 4 A Miller clamp, UVLO, thermal shutdown, and configurable interlocking - designed for high-reliability 600/1200 V inverter stages in industrial motor drives and UPS systems.
For engineers reviewing the STGAP2SICDTR datasheet, STGAP2SICDTR pinout, STGAP2SICDTR application, or STGAP2SICDTR equivalent, key selection criteria include isolation rating (3.5 kVRMS), dual-channel timing matching (<20 ns), independent gate resistor optimization, and safe-state behavior during UVLO, standby, or thermal fault conditions.
Technical Context
The device implements two fully isolated gate driving channels with independent floating supplies (VH_A/VH_B) referenced to GNDISO_A/GNDISO_B, enabling half-bridge and three-phase inverter topologies with ±1700 V differential floating ground tolerance. Each channel integrates rail-to-rail output buffers, dedicated GOFF/GON/CLAMP terminals, and programmable interlocking via the iLOCK pin.
Its protection architecture includes active UVLO on VH_x (14.6–16.4 V turn-on, 600–950 mV hysteresis), thermal shutdown at 170 °C with 20 °C hysteresis, and deglitch-filtered logic inputs (20–40 ns). Standby mode reduces VDD and VH_x quiescent current to 40–80 µA and 400–550 µA respectively while forcing outputs into safe state (GOFF active, GON high-Z).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Voltage (VISO) | 3.5 kVRMS - certified per UL 1577 and IEC 60747-17 for reinforced insulation in safety-critical power conversion. |
| Output Drive Current | 4 A sink/source @ 25 °C - enables fast switching of high-Qg SiC MOSFETs up to 1 MHz with low RDS_ON (1.1–1.5 Ω). |
| Propagation Delay | 75 ns typ. - ensures precise PWM timing alignment between channels for reduced dead-time uncertainty in inverters. |
| CMTI | 100 V/ns - maintains signal integrity under fast dV/dt transients common in SiC-based 1200 V bus systems. |
| Miller Clamp Threshold | 1.3–2.6 V - actively clamps gate voltage during commutation to suppress false turn-on in half-bridge configurations. |
| Operating Junction Temp | −40 to +125 °C - supports industrial ambient environments without derating below 125 °C. |
| Package Thermal Resistance | Rth(JA) = 52 °C/W - requires careful PCB copper pour and via placement to sustain full 4 A output at elevated ambient. |
Pinout & Package
STGAP2SICDTR uses a Wide Body SO-36W package (12.8 × 12.8 mm, 2.65 mm height) with creepage/clearance ≥8 mm and CTI ≥400 V, rated for basic insulation per IEC 60747-17.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, GND | Control logic supply | 5.5 V max logic rail; powers internal logic, UVLO, and deglitch filters - requires local 100 nF + 1–10 µF bypassing. |
| INA, INB | Channel A/B input | 3.3/5 V TTL/CMOS-compatible with hysteresis - controls GON_A/GON_B high-side sourcing when active high. |
| SD, BRAKE | Protection inputs | Active-low shutdown and brake signals - force safe state (GOFF active) independently of channel logic. |
| iLOCK | Interlock config | Connect to VDD to enable shoot-through prevention; tie to GND to disable and allow parallel channel operation. |
| VH_A, GNDISO_A | Channel A gate supply | Floating 26 V max positive rail - powers GOFF_A, GON_A, CLAMP_A; both GNDISO_A pins must be shorted. |
| VH_B, GNDISO_B | Channel B gate supply | Independent floating 26 V rail - enables asymmetric gate drive and phase-shifted control in multi-level topologies. |
| GON_A, GOFF_A, CLAMP_A | Channel A outputs | Separate source/sink/clamp terminals - allow independent gate resistor tuning for optimized dV/dt and EMI control. |
| GON_B, GOFF_B, CLAMP_B | Channel B outputs | Matched timing and drive strength to Channel A - ensures <20 ns channel-to-channel matching for balanced switching. |
Key Features
| Feature | Design Value |
|---|---|
| Dual isolated gate drivers | Two independent 4 A channels with separate VH/GNDISO supplies - supports half-bridge, 3-phase, and multi-level SiC inverter designs. |
| Configurable interlocking | Hardware-enforced shoot-through prevention via iLOCK pin - eliminates software dependency for critical safety in motor control. |
| Miller clamp with 2 V threshold | Clamps gate voltage below 2.6 V during high dV/dt transitions - prevents parasitic turn-on without external components. |
| Safe-state architecture | Automatic GOFF activation during UVLO, thermal shutdown, or VDD loss - guarantees fail-safe MOSFET turn-off in fault conditions. |
| Standby mode with sub-100 µA draw | Reduces total system idle power by >95% - ideal for battery-backed or energy-sensitive industrial automation systems. |
Applications
| Industrial Motor Drives | Uninterruptible Power Supplies (UPS) |
|---|---|
|
Use Scenario: 15–75 kW variable-frequency drives for pumps, compressors, and conveyors using 1200 V SiC MOSFETs. IC Role / Device Role / Timing Role: Dual-channel isolated gate driver providing matched 75 ns propagation delay and 4 A peak current to control high-side/low-side switches in three-phase inverter legs. Use Value: Enables >20 kHz switching with minimal dead-time penalty and robust noise immunity (100 V/ns CMTI) in electrically noisy factory environments. |
Use Scenario: Online double-conversion UPS systems requiring fast transfer, high efficiency, and galvanic isolation between control and power stages. IC Role / Device Role / Timing Role: Gate driver for SiC-based DC-AC inverter stage, managing synchronous rectification and bidirectional power flow with thermal fault response. Use Value: Integrated UVLO, thermal shutdown, and safe-state behavior ensure continuous load protection during grid anomalies or cooling failures. |
| Battery Charging Systems | Induction Heating |
|
Use Scenario: High-power EV DC fast chargers (150–350 kW) with SiC-based AC-DC PFC and DC-DC stages. IC Role / Device Role / Timing Role: Isolated driver for interleaved totem-pole PFC and LLC resonant converter primary-side switches. Use Value: Separate GOFF/GON pins allow independent gate resistance tuning to balance conduction losses and EMI across paralleled SiC devices. |
Use Scenario: Solid-state induction cooktops and industrial heating systems operating at 20–100 kHz with 600 V SiC half-bridges. IC Role / Device Role / Timing Role: Gate driver for resonant inverter leg, leveraging Miller clamp to suppress gate oscillation during zero-voltage switching transitions. Use Value: 4 A drive strength sustains fast gate charging at high frequency while maintaining <30 ns rise/fall times under 4.7 nF load. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8273BD-IS | 3.75 kVRMS isolation, 4 A drive, but only 35 ns propagation delay and no Miller clamp. | Lacks integrated Miller clamp and interlocking - requires external circuitry for shoot-through prevention in half-bridge use. | Preferred where ultra-low propagation delay dominates over integrated protection features. |
| UCC5870QDWJRQ1 | 5.7 kVRMS isolation, 10 A drive, but single-channel with external bootstrap or isolated supply needed for dual operation. | Requires two devices plus external bias supplies for dual-channel implementation - increases BOM count and layout complexity. | Chosen when higher peak current (>4 A) or automotive AEC-Q100 qualification is mandatory. |
Compared with Si8273BD-IS and UCC5870QDWJRQ1, STGAP2SICDTR uniquely integrates dual-channel isolation, Miller clamp, interlocking, and standby in one SO-36W package - reducing system-level design effort for SiC inverter applications requiring functional safety and compactness.
Availability
STGAP2SICDTR is available at Aetrix Electronics and suitable for industrial motor drives, uninterruptible power supplies, and SiC-based battery charging systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for STGAP2SICDTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, analog, microcontrollers, and automotive-grade ICs.
STGAP2SICDTR belongs to ST's STGAP family of isolated gate drivers, engineered specifically for high-efficiency, high-reliability SiC and GaN power systems demanding robust isolation, fast switching, and integrated protection.
FAQ
What is the maximum recommended gate supply voltage (VH_x) for STGAP2SICDTR?
The absolute maximum VH_x is 28 V, but the recommended operating condition is ≤26 V (VH_x vs. GNDISO_x). Exceeding 26 V risks violating safe operating area limits and may trigger internal overvoltage protection. The UVLO turn-on threshold is 14.6–16.4 V, ensuring reliable startup with adequate margin above typical 15–18 V SiC gate drive rails.
How does the interlocking function behave when disabled via the iLOCK pin?
When iLOCK is tied to GND, interlocking is disabled and both channels operate independently - allowing simultaneous high-side activation (e.g., for synchronous rectification or multi-level topologies). The truth table confirms that with iLOCK = GND and INA = INB = HIGH, both GOUT_A and GOUT_B go HIGH, unlike the default shoot-through-protected behavior.
Can STGAP2SICDTR drive both unipolar and bipolar gate configurations?
Yes - the separate GOFF and GON outputs per channel support both unipolar (e.g., VH_A to GNDISO_A only) and bipolar (e.g., VH_A to VL_A with negative turn-off) configurations. Figure 5 in the datasheet explicitly shows both topologies, and the CLAMP_A/CLAMP_B pins provide active Miller clamping regardless of supply scheme.
What happens to the outputs during thermal shutdown?
At junction temperature ≥170 °C, STGAP2SICDTR forces all outputs into safe state: GOFF_A/GOFF_B go active (low), GON_A/GON_B enter high-impedance, and CLAMP_A/CLAMP_B remain inactive. Operation resumes only after junction temperature falls below 150 °C (170 °C − 20 °C hysteresis), preventing premature restart during thermal recovery.
STGAP2SICDTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 36-BSOP (0.295", 7.50mm Width), 32 Leads
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Number of Channels:
- 2
- Voltage - Isolation:
- 6000Vrms
- Common Mode Transient Immunity (Min):
- 100V/ns
- Propagation Delay tpLH / tpHL (Max):
- 90ns, 90ns
- Pulse Width Distortion (Max):
- -
- Rise / Fall Time (Typ):
- 30ns, 30ns
- Current - Output High, Low:
- 4A, 4A
- Current - Peak Output:
- 4A
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 3.1V ~ 5.5V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 36-SO
- Approval Agency:
- UL, VDE
STGAP2SICDTR FAQ
1.How can I place an order for STGAP2SICDTR through Aetrix?
Please submit a Request for Quotation (RFQ) for STGAP2SICDTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STGAP2SICDTR reliable?
The price and inventory of STGAP2SICDTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STGAP2SICDTR is usually 5 days.
3.What payment methods are accepted for STGAP2SICDTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STGAP2SICDTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STGAP2SICDTR?
STGAP2SICDTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STGAP2SICDTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STGAP2SICDTR?
For technical support, including STGAP2SICDTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STGAP2SICDTR requirements.
6.How does Aetrix verify that STGAP2SICDTR is sourced from the original manufacturer or authorized distributors?
All STGAP2SICDTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STGAP2SICDTR meets industry standards.
7.What is the process for return or replacement of STGAP2SICDTR?
All STGAP2SICDTR units undergo pre-shipment inspection (PSI). If there is an issue with STGAP2SICDTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STGAP2SICDTR part is unused and in its original packaging.
Return procedure for STGAP2SICDTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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