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Home > Products > Isolators > Isolators - Gate Drivers

STMicroelectronics STGAP2SICS

Name: STGAP2SICS
Brand: STMicroelectronics
SKU: STGAP2SICS
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: STGAP2SICS

Manufacturer:: STMicroelectronics

Category:: Isolators - Gate Drivers

Package:: 8-SOIC (0.295", 7.50mm Width)

Datasheet:: STGAP2SICS.pdf

Description:: DIGITAL ISO 5KV 1CH GATE DVR 8SO

Quantity:: RFQ Add To RFQ list

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Product details

Overview

STGAP2SICS from STMicroelectronics is a galvanically isolated single-channel gate driver IC optimized for SiC MOSFETs in high-speed, high-voltage power stages. It delivers 4 A sink/source drive capability, 100 V/ns CMTI, 75 ns max input-output propagation delay, and integrated Miller clamp (V_CLAMPth = 2 V typ), UVLO (V_HON = 15.5 V), and thermal shutdown (T_SD = 170 °C). It enables robust half-bridge control in 600–1200 V industrial inverters.

For engineers reviewing the STGAP2SICS datasheet, STGAP2SICS pinout, STGAP2SICS application, or STGAP2SICS equivalent, key selection criteria include isolation rating (V_ISO = 3.5 kV_RMS), dual-input polarity control for hardware interlock, standby mode (I_QDDSBY = 40–65 µA), and SO-8W package compatibility with high-power SiC gate-drive layouts.

Technical Context

The STGAP2SICS implements reinforced galvanic isolation per IEC 60747-17 and UL 1577, with VIORM = 1.2 kV_PEAK and VIOTM = 5.0 kV_PEAK. Its dual-input architecture (IN+, IN−) supports active-high/active-low logic and enables hardware-based cross-conduction prevention independent of controller firmware.

Two configurable output topologies are supported: (1) separate GON/GOFF pins for independent turn-on/turn-off resistor tuning, and (2) single GOUT + CLAMP pin for Miller current suppression during fast commutation. Both modes maintain rail-to-rail output swing up to 26 V and operate across −40 °C to +125 °C ambient.

Key Specifications

Parameter	Value and Actual Design Meaning
CMTI	100 V/ns - Ensures reliable operation under fast dv/dt noise in SiC-based 1 MHz switching converters.
Propagation delay	75 ns max - Enables precise PWM timing control with <20 ns pulse width distortion for high-fidelity gate signals.
Output drive	4 A sink/source - Directly drives high-Qg SiC MOSFETs without external buffers in 10–50 kW motor drives.
Isolation voltage	V_ISO = 3.5 kV_RMS - Meets reinforced insulation requirements for 600–1200 V DC bus systems per IEC 61800-5-1.
UVLO threshold	V_HON/V_Hoff = 15.5 V / 14.8 V - Optimized for SiC gate thresholds; prevents partial turn-on during low-VH brownout.
Miller clamp	V_CLAMPth = 2 V - Actively clamps gate below Miller plateau to suppress spurious turn-on in half-bridge leg shoot-through.
Thermal shutdown	T_SD = 170 °C - Protects isolation barrier integrity during overload or cooling failure in enclosed industrial enclosures.
Standby current	I_QDDSBY = 40–65 µA - Reduces idle power in battery-backed UPS or always-on PFC stages without disabling protection functions.

Pinout & Package

STGAP2SICS is housed in a wide-body SO-8W package (8.7 mm × 7.6 mm, 2.65 mm height) with creepage/clearance ≥8 mm and CTI ≥400 V, certified to IEC 60747-17 for reinforced insulation.

Pin	Circuit Role	Design Meaning
1	VDD	Logic supply (3.1–5.5 V); powers internal control logic and level shifter - requires local 100 nF + 1 µF bypassing.
2	IN+	Active-high logic input; used with IN− for HW interlock - deglitched (20–40 ns filter) against EMI-induced false triggers.
3	IN−	Active-low logic input; complements IN+ for fault-tolerant enable/disable - enables dead-time-free complementary drive.
4	GND	Logic ground reference; must be separated from GNDISO to preserve isolation barrier integrity.
5	VH	High-side gate drive supply (up to 26 V); powers output stage - requires dedicated 100 nF + 1–10 µF local decoupling.
6	GOUT / GON	Single-output config: rail-to-rail gate driver output (4 A); Separate-output config: source output only - directly connects to SiC MOSFET gate.
7	CLAMP / GOFF	Single-output config: Miller clamp output (4 A sink, V_CLAMPth = 2 V); Separate-output config: sink output only - provides active pull-down during Miller region.
8	GNDISO	Isolated floating ground; return path for VH and gate outputs - must be routed on isolated PCB layer with no underlying copper.

Key Features

Feature	Design Value
Dual-input polarity control	IN+/IN− truth table enables hardware-level cross-conduction prevention - eliminates reliance on MCU timing margins or software dead-time insertion.
Configurable output topology	Selectable between GON/GOFF separation (for independent R_g,on/R_g,off) or GOUT+CLAMP (for Miller spike suppression) - reduces BOM count across inverter designs.
Reinforced isolation certification	IEC 60747-17 certified (Cert #40057398) and UL 1577 recognized - qualifies for safety-critical industrial drives without additional system-level isolation testing.
Integrated thermal shutdown	170 °C trip with 20 °C hysteresis - maintains safe state until junction cools, preventing thermal runaway in sealed motor drive enclosures.
Low-power standby mode	Enters safe state (GOFF active, GON high-Z) with <65 µA VDD quiescent current - enables energy-efficient always-on monitoring in smart UPS systems.

Applications

Industrial Motor Inverters

SiC-Based Battery Chargers

Use Scenario: 15–75 kW variable-frequency drives for HVAC compressors and conveyor systems using 1200 V SiC MOSFETs.

IC Role / Device Role / Timing Role: Isolated gate driver providing 4 A peak current, 75 ns timing accuracy, and Miller clamp to prevent shoot-through during 50–100 kHz PWM.

Use Value: Enables >99% efficiency at full load by minimizing switching losses and eliminating external desaturation detection circuitry.

Use Scenario: Bidirectional 3-phase AC/DC + DC/DC battery chargers for EVSE with 800 V SiC stacks and active rectification.

IC Role / Device Role / Timing Role: High-CMTI isolated driver controlling high-side SiC switches in totem-pole PFC and isolated DC-DC stages.

Use Value: Supports 1 MHz switching with stable gate control under 100 V/ns common-mode transients from fast SiC switching edges.

Induction Heating Systems

Uninterruptible Power Supplies

Use Scenario: 5–20 kW resonant inverters driving induction coils in industrial metal heating, requiring fast zero-voltage switching.

IC Role / Device Role / Timing Role: Gate driver with <20 ns pulse width distortion and dual-input interlock ensuring precise phase alignment between half-bridge legs.

Use Value: Eliminates need for external gate resistors tuned per temperature, maintaining ZVS across −25 °C to +70 °C ambient.

Use Scenario: Online double-conversion UPS with 400 V DC link and SiC-based inverter stage delivering clean 230 VAC output.

IC Role / Device Role / Timing Role: Isolated driver enabling fast transfer (<10 ms) between utility and battery modes while maintaining gate control integrity.

Use Value: Standby mode reduces idle power by >90% vs. active gate drivers, extending runtime in backup-only operation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar isolated SiC gate driver applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si827x (Silicon Labs)	Higher CMTI (150 V/ns), but lower drive strength (2.5 A), no integrated Miller clamp, and no dual-input interlock logic.	Suitable for lower-power SiC modules (<10 kW); requires external clamp circuit and MCU-managed dead time.	Prefer when ultra-high noise immunity is critical and gate drive current demand is ≤2.5 A.
UCC5870-Q1 (TI)	Automotive-qualified AEC-Q100, higher UVLO (16.5 V), but larger SOIC-16 package and no standby mode.	Targeted at traction inverters; lacks industrial thermal derating curves and layout-optimized SO-8W footprint.	Choose for automotive-grade reliability where ISO 26262 ASIL-B compliance is mandatory.

Compared with Si827x and UCC5870-Q1, STGAP2SICS uniquely combines 4 A drive, integrated Miller clamp, dual-input hardware interlock, and SO-8W industrial layout compatibility - making it optimal for cost-sensitive, high-power industrial SiC inverters requiring minimal external components.

Availability

STGAP2SICS is available at Aetrix Electronics and suitable for industrial motor drives, SiC battery chargers, and uninterruptible power supplies requiring stable component supply, long-term lifecycle support, and traceable sourcing for production ramp-up.

Supply support for STGAP2SICS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, power, microcontroller, and sensor solutions for industrial, automotive, and consumer markets.

STGAP2SICS belongs to ST's STGAP family of isolated gate drivers, engineered specifically for high-efficiency SiC and GaN power systems demanding high CMTI, fast propagation, and integrated protection in compact packages.

FAQ

What is the purpose of the dual IN+ and IN− inputs?

The IN+ and IN− pins provide hardware-level polarity selection and cross-conduction prevention. When both are asserted (IN+ = HIGH, IN− = HIGH), the device enters standby mode. Any other combination drives the output according to the truth table - enabling fail-safe operation even if the MCU freezes or loses communication, without requiring software intervention.

How does the Miller clamp function protect SiC MOSFETs?

The CLAMP pin monitors the gate voltage during turn-off. When gate voltage falls below V_CLAMPth (2 V typ), the internal clamp switch activates, creating a low-impedance path to GNDISO. This actively discharges the Miller capacitance (C_GD) and prevents unintended turn-on caused by high dv/dt across the drain-source during high-side switching in half-bridge configurations.

Can STGAP2SICS drive both unipolar and bipolar gate voltages?

Yes. With VH referenced to GNDISO, the device supports unipolar drive (e.g., 0 V / +20 V). By adding a negative auxiliary supply (VL) referenced to GNDISO, it enables bipolar drive (e.g., −5 V / +20 V) - improving SiC MOSFET short-circuit ruggedness and reducing switching losses in high-reliability industrial inverters.

What layout practices are critical for maintaining CMTI performance?

To sustain 100 V/ns CMTI, place 100 nF ceramic capacitors directly at VDD-GND and VH-GNDISO pins, route GNDISO on a dedicated inner layer with no copper beneath the IC, avoid traces crossing the isolation barrier, and use multiple vias to connect VH/GNDISO to internal planes - all per ST's layout guidelines in DS13402 Section 8.

STGAP2SICS Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: -

Package/Case:: 8-SOIC (0.295", 7.50mm Width)

Packaging:: Tube

Product Status:: Active

Technology:: Capacitive Coupling

Number of Channels:: 1

Voltage - Isolation:: 5000Vrms

Common Mode Transient Immunity (Min):: 100V/ns

Propagation Delay tpLH / tpHL (Max):: 90ns, 90ns

Pulse Width Distortion (Max):: 20ns

Rise / Fall Time (Typ):: 30ns, 30ns

Current - Output High, Low:: 4A, 4A

Current - Peak Output:: 4A

Voltage - Forward (Vf) (Typ):: -

Current - DC Forward (If) (Max):: -

Voltage - Output Supply:: 3V ~ 5.5V

Grade:: -

Qualification:: -

Operating Temperature:: -40°C ~ 125°C

Mounting Type:: Surface Mount

Supplier Device Package:: 8-SO

Approval Agency:: UL

STGAP2SICS FAQ

1.How can I place an order for STGAP2SICS through Aetrix?

Please submit a Request for Quotation (RFQ) for STGAP2SICS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for STGAP2SICS reliable?

The price and inventory of STGAP2SICS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STGAP2SICS is usually 5 days.

3.What payment methods are accepted for STGAP2SICS?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STGAP2SICS transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for STGAP2SICS?

STGAP2SICS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your STGAP2SICS order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for STGAP2SICS?

For technical support, including STGAP2SICS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STGAP2SICS requirements.

6.How does Aetrix verify that STGAP2SICS is sourced from the original manufacturer or authorized distributors?

All STGAP2SICS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STGAP2SICS meets industry standards.

7.What is the process for return or replacement of STGAP2SICS?

All STGAP2SICS units undergo pre-shipment inspection (PSI). If there is an issue with STGAP2SICS, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The STGAP2SICS part is unused and in its original packaging.

Return procedure for STGAP2SICS:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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