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STMicroelectronics STGAP2SICSCTR
- Part No.:
- STGAP2SICSCTR
- Manufacturer:
- STMicroelectronics
- Category:
- Isolators - Gate Drivers
- Package:
- 8-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
STGAP2SICSCTR.pdf
- Description:
- DIGITAL ISO 5KV 1CH GATE DVR 8SO
- Quantity:
- Payment:
- Shipping:
Inventory:855
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Product details
Overview
STGAP2SICSCTR from STMicroelectronics is a galvanically isolated single-channel gate driver IC optimized for SiC MOSFETs in high-speed, high-voltage half-bridge topologies. It delivers 4 A sink/source peak output current, 100 V/ns CMTI, 75 ns max input-output propagation delay, and integrated Miller clamp (CLAMP pin), UVLO (15.5 V turn-on), and thermal shutdown (170 °C). It enables robust motor inverters and 600–1200 V power converters.
For engineers reviewing the STGAP2SICSCTR datasheet, STGAP2SICSCTR pinout, STGAP2SICSCTR application, or STGAP2SICSCTR equivalent, key selection criteria include isolation rating (3.5 kVRMS), dual-input polarity control for hardware interlock, standby mode quiescent current (400 µA on VH), and SO-8W wide-body package suitability for >1.2 kVPEAK systems.
Technical Context
The device implements reinforced galvanic isolation per IEC 60747-17 and UL 1577, with VIORM = 1.2 kVPEAK and VISO = 3.5 kVRMS. Its dual-input architecture (IN+, IN−) supports active-high/active-low logic and enables hardware-based cross-conduction prevention in inverter legs.
Two configurable output modes are supported: (1) separate GON/GOFF pins for independent turn-on/turn-off resistor tuning, and (2) single GOUT + CLAMP pin for Miller spike suppression during fast commutation. Both modes maintain rail-to-rail 4 A drive capability and <20 ns pulse width distortion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CMTI | 100 V/ns - Ensures reliable operation under fast dv/dt transients in SiC-based 1200 V inverters. |
| Propagation Delay | 75 ns max - Enables precise PWM timing control up to 1 MHz switching frequency. |
| VH UVLO Threshold | 15.5 V typ - Matches SiC MOSFET gate drive requirements and prevents partial turn-on. |
| Output Current | 4 A sink/source - Drives large gate charges of 600–1200 V SiC MOSFETs without external buffers. |
| Isolation Voltage | 3.5 kVRMS - Certified for basic insulation in industrial motor drives and UPS systems. |
| Miller Clamp Threshold | 2.0 V typ - Activates CLAMP at safe gate voltage level to suppress unintended turn-on in half-bridges. |
| Standby IQ | 400 µA on VH - Reduces idle power in battery-backed or energy-sensitive applications. |
Pinout & Package
STGAP2SICSCTR is housed in a wide-body SO-8W package (8.7 mm × 5.9 mm, 2.65 mm height) with reinforced creepage/clearance (8 mm) and CTI ≥ 400 V for industrial safety compliance.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | VDD | Logic supply input (3.1–5.5 V); powers internal control circuitry and level shifter. |
| 2 | IN+ | Active-high logic input; used with IN− for differential control and HW interlock. |
| 3 | IN− | Active-low logic input; enables noise-immune signal reception and fault-safe default state. |
| 4 | GND | Logic ground reference; must be decoupled with 100 nF ceramic capacitor near pin. |
| 5 | VH | High-side gate drive supply (up to 26 V); powers floating output stage and UVLO monitoring. |
| 6 | GOUT / GON | Source/sink output (configurable); delivers 4 A rail-to-rail drive to SiC MOSFET gate. |
| 7 | CLAMP / GOFF | Miller clamp output (in CLAMP config) or dedicated sink output (in separate config); clamps gate below 2.0 V to prevent dv/dt-induced turn-on. |
| 8 | GNDISO | Isolated gate drive ground; forms barrier with VDD/GND; requires dedicated plane and local 100 nF bypass. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-input polarity control | IN+/IN− inputs enable hardware interlock and eliminate need for external logic to prevent shoot-through. |
| Configurable output topology | Selectable between single-output+CLAMP or separate GON/GOFF-reduces BOM count across inverter designs. |
| Integrated Miller clamp | CLAMP pin activates at 2.0 V threshold to short gate to GNDISO, suppressing Miller-induced false turn-on. |
| Thermal shutdown with hysteresis | Shuts down at 170 °C junction temperature; resumes operation only after cooling by ≥20 °C. |
| Low-power standby mode | Enters sub-500 µA quiescent state when both inputs held high >280 µs; wakes in <35 µs. |
Applications
| Industrial Motor Inverters | SiC-Based Battery Chargers |
|---|---|
|
Use Scenario: Driving 1200 V SiC MOSFET half-bridges in factory automation servo drives operating at 50–100 kHz. IC Role / Device Role / Timing Role: Isolated gate driver providing 4 A peak current, 75 ns timing accuracy, and CMTI immunity to ensure clean switching under 100 V/ns bus transients. Use Value: Eliminates external Miller clamp diodes and reduces gate loop inductance via SO-8W layout-optimized pinout. |
Use Scenario: Bidirectional AC/DC and DC/DC stages in EV fast-charging stations using 600 V SiC modules. IC Role / Device Role / Timing Role: High-CMTI isolated driver enabling >100 kHz ZVS operation while maintaining safe gate control under high dv/dt. Use Value: Integrated UVLO (15.5 V) prevents partial turn-on of SiC devices during brown-out conditions. |
| Induction Heating Systems | UPS Inverter Stages |
|
Use Scenario: Resonant LLC inverters driving induction coils at 20–80 kHz with rapid load transients. IC Role / Device Role / Timing Role: Gate driver with <20 ns pulse width distortion and deglitched inputs ensures consistent dead-time control. Use Value: Standby mode cuts idle power by >90%, critical for always-on standby circuits in consumer-grade units. |
Use Scenario: Online double-conversion UPS delivering clean 50/60 Hz sine wave with <1% THD under nonlinear loads. IC Role / Device Role / Timing Role: Reinforced-isolation driver (3.5 kVRMS) meets IEC 62040-1 safety requirements for mains-connected inverters. Use Value: Dual input pins allow direct connection to MCU PWM outputs without level-shifting or glue logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar isolated SiC gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8273BD-IS | 3.75 kVRMS isolation, 4 A drive, but no integrated Miller clamp; uses external R-C network for clamp function. | Lacks dedicated CLAMP pin-requires PCB area and design effort to replicate Miller protection. | Preferred where cost sensitivity outweighs layout simplicity and where external clamp tuning is acceptable. |
| UCC5390SCD | 3.75 kVRMS, 4 A, includes Miller clamp, but only 50 V/ns CMTI and no dual-input interlock logic. | Lower CMTI limits use in 1200 V SiC systems with fast bus transients; lacks hardware shoot-through prevention. | Appropriate for lower-dv/dt 600 V SiC or GaN applications where interlock is handled in firmware. |
Compared with Si8273BD-IS and UCC5390SCD, STGAP2SICSCTR uniquely combines 100 V/ns CMTI, integrated Miller clamp, dual-input hardware interlock, and 3.5 kVRMS certified isolation-making it optimal for high-reliability 1200 V SiC motor drives and industrial UPS.
Availability
STGAP2SICSCTR is available at Aetrix Electronics and suitable for industrial motor inverters, SiC-based battery chargers, and UPS inverter stages requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for STGAP2SICSCTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, power, microcontroller, and sensor solutions for industrial, automotive, and consumer markets.
STGAP2SICSCTR belongs to ST's STGAP family of isolated gate drivers-engineered specifically for high-efficiency, high-reliability SiC and GaN power systems demanding reinforced isolation, fast timing, and integrated protection.
FAQ
What is the purpose of the CLAMP pin in STGAP2SICSCTR?
The CLAMP pin provides active Miller current suppression by creating a low-impedance path from the MOSFET gate to GNDISO when gate voltage falls below 2.0 V. This prevents unintended turn-on during high dv/dt commutation in half-bridge configurations-critical for SiC MOSFETs with low threshold voltages and high CGD capacitance.
How does the dual-input (IN+/IN−) architecture improve system reliability?
IN+ and IN− accept complementary logic signals and implement hardware-level interlock: only one input can be asserted at a time to enable GON or GOFF. If both go high (standby) or both low (fault), the output defaults to safe state-eliminating software-dependent shoot-through protection and improving fault tolerance in controller failure scenarios.
Can STGAP2SICSCTR drive both unipolar and bipolar gate voltages?
Yes. With VH referenced to GNDISO, the driver supports unipolar (0 V to +26 V) or bipolar (−5 V to +26 V) gate drive by adding an external negative bias supply (VL) to GNDISO. The datasheet Figure 7 shows both configurations, and the SO-8W layout accommodates separate VL routing without compromising isolation.
What thermal derating applies to STGAP2SICSCTR at elevated ambient temperatures?
At 125 °C ambient, the maximum allowable total safety-limiting power (PSO + PSI) drops to ~0.4 mW per the thermal derating curve in DS13402 page 9. This restricts continuous output current to ~12 mA at VH = 26 V. Designers must use heatsinking, airflow, or reduced duty cycle to maintain TJ ≤ 125 °C in high-temp enclosures.
STGAP2SICSCTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Number of Channels:
- 1
- Voltage - Isolation:
- 5000Vrms
- Common Mode Transient Immunity (Min):
- 100V/ns
- Propagation Delay tpLH / tpHL (Max):
- 90ns, 90ns
- Pulse Width Distortion (Max):
- 20ns
- Rise / Fall Time (Typ):
- 30ns, 30ns
- Current - Output High, Low:
- 4A, 4A
- Current - Peak Output:
- 4A
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 3V ~ 5.5V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SO
- Approval Agency:
- UL
STGAP2SICSCTR FAQ
1.How can I place an order for STGAP2SICSCTR through Aetrix?
Please submit a Request for Quotation (RFQ) for STGAP2SICSCTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STGAP2SICSCTR reliable?
The price and inventory of STGAP2SICSCTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STGAP2SICSCTR is usually 5 days.
3.What payment methods are accepted for STGAP2SICSCTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STGAP2SICSCTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STGAP2SICSCTR?
STGAP2SICSCTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STGAP2SICSCTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STGAP2SICSCTR?
For technical support, including STGAP2SICSCTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STGAP2SICSCTR requirements.
6.How does Aetrix verify that STGAP2SICSCTR is sourced from the original manufacturer or authorized distributors?
All STGAP2SICSCTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STGAP2SICSCTR meets industry standards.
7.What is the process for return or replacement of STGAP2SICSCTR?
All STGAP2SICSCTR units undergo pre-shipment inspection (PSI). If there is an issue with STGAP2SICSCTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STGAP2SICSCTR part is unused and in its original packaging.
Return procedure for STGAP2SICSCTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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